Abstract: Gamma curve correction circuitry includes first (24-1,2 . . . 11) and second (24-12,13 . . . 22) groups of gamma correction buffers and corresponding DACs (28-1,2 . . . 22). Each buffer has an input coupled to an output of a corresponding DAC, respectively, and an output coupled by a corresponding output conductor, respectively, to a corresponding resistor string tap point. A midrange voltage (V30) is produced with a value approximately midway between a first voltage (VDD) and a second voltage (GND) and is coupled to provide power to the first and second groups of buffers. The first voltage is coupled to a first voltage terminal of a first buffer (24-11) of the first group. A second voltage terminal of the first buffer is coupled to the midrange voltage. The midrange voltage is coupled to a first voltage terminal of a first buffer (24-12) of the second group. A second voltage terminal of the first buffer of the second group is coupled to the second voltage.

Abstract: A differential amplifier (1D) includes circuitry (5,R1,R2,52) coupling a common mode component of an input voltage (Vin+?Vin?) to a maximum voltage selector circuit (53) that produces an internal voltage (VRAIL-TOP) equal to the larger of a first supply voltage (VREG) and the common mode component. An input amplifier circuit (46) of the differential amplifier is powered by the internal voltage. The input voltage (Vin+?Vin?) is coupled to inputs (41A,B) of the input amplifier circuit (46). Outputs (64A,B) of the input amplifier circuit (46) are amplified by an output amplifier (50).

Abstract: Gamma curve correction circuitry includes first (24-1,2 . . . 11) and second (24-12,13 . . . 22) groups of gamma correction buffers and corresponding DACs (28-1,2 . . . 22). Each buffer has an input coupled to an output of a corresponding DAC, respectively, and an output coupled by a corresponding output conductor, respectively, to a corresponding resistor string tap point. A midrange voltage (V30) is produced with a value approximately midway between a first voltage (VDD) and a second voltage (GND) and is coupled to provide power to the first and second groups of buffers. The first voltage is coupled to a first voltage terminal of a first buffer (24-11) of the first group. A second voltage terminal of the first buffer is coupled to the midrange voltage. The midrange voltage is coupled to a first voltage terminal of a first buffer (24-12) of the second group. A second voltage terminal of the first buffer of the second group is coupled to the second voltage.

Abstract: A differential amplifier (1D) includes circuitry (5,R1,R2,52) coupling a common mode component of an input voltage (Vin+?Vin?) to a maximum voltage selector circuit (53) that produces an internal voltage (VRAIL-TOP) equal to the larger of a first supply voltage (VREG) and the common mode component. An input amplifier circuit (46) of the differential amplifier is powered by the internal voltage. The input voltage (Vin+?Vin?) is coupled to inputs (41A,B) of the input amplifier circuit (46). Outputs (64A,B) of the input amplifier circuit (46) are amplified by an output amplifier (50).

Abstract: A gamma reference voltage generator (10B) for an LCD display includes a control interface logic circuit (48) having an output bus coupled to inputs of a first register (46) having outputs coupled to inputs of a second register (42) the outputs of which are coupled to corresponding inputs of plurality of DACs (28). The control interface logic circuit receives gray scale codes representative of gamma reference voltages and transfers the codes via the output bus into the first register and controls further transfer of the codes to inputs of the DACs to instantaneously or rapidly update gamma correction voltages applied to the LCD display.

Abstract: An operational amplifier includes an input stage for producing a voltage signal in response to an input signal. An output stage includes an output transistor having a source coupled to a supply voltage and a gate coupled to receive the voltage signal. An output cascode transistor has a source coupled to a drain of the output transistor and a drain coupled to an output conductor. A gate control amplifier includes an input stage including a first input transistor having a control electrode coupled to the source of the output cascode transistor and an active load transistor, the input transistor and the active load transistor being coupled to a gate of the output cascode transistor. The gate control amplifier also includes a feedback amplifier having an input coupled to the source of the output cascode transistor and an output coupled to a control electrode of the active load transistor.

Abstract: A complementary output stage in integrated circuit includes a P-channel transistor (MP1) the segmented into a first group of sections (MP1-1,2 . . . 12) and an N-channel transistor (MN1) segmented into a second group of sections (MN1-1,2 . . . 12). The sections of the first group are disposed in a plurality of N-type well regions (35), respectively, and the sections of the second group are disposed in a plurality of P-type well regions (36), respectively. The sections of the first group are alternately located with respect to the sections of the second group so as to form an interdigitated output stage area of the integrated circuit including the P-channel transistor (MP1) and the N-channel transistor (MN1) so that the higher amount of heat normally generated in the N-channel transistor is dissipated over the entire interdigitated output stage area and reduces peak temperatures in the N-channel transistor.

Abstract: Over-current protection is accomplished in an output transistor (MP) of an electronic circuit wherein an input signal (Vgatedrive) Is Applying to a first conductor (19) coupled to a gate of the output transistor to cause an output current (Iout) to flow through the output transistor and an output terminal (11) of the electronic circuit. A limit voltage (VLIMIT) who is applied to an input (21) of a voltage clamping circuit (18) to cause a clamping current to flow in the first conductor (19) as needed to prevent the magnitude of the input signal (Vgatedrive) from being less than the magnitude of the limit voltage (VLIMIT) so that the output current (Iout) is limited to a maximum current limit determined by the limit voltage (VLIMIT).

Abstract: Over-current protection is accomplished in an output transistor (MP) of an electronic circuit wherein an input signal (Vgatedrive) Is Applying to a first conductor (19) coupled to a gate of the output transistor to cause an output current (Iout) to flow through the output transistor and an output terminal (11) of the electronic circuit. A limit voltage (VLIMIT) who is applied to an input (21) of a voltage clamping circuit (18) to cause a clamping current to flow in the first conductor (19) as needed to prevent the magnitude of the input signal (Vgatedrive) from being less than the magnitude of the limit voltage (VLIMIT) so that the output current (Iout) is limited to a maximum current limit determined by the limit voltage (VLIMIT).

Abstract: A differential input circuit (1) includes circuitry for generating slew boost currents to be supplied to an output stage of an operational amplifier. The differential input circuit (1) includes a differential current steering circuit including a first transistor (M2) having a gate coupled to receive a first input signal (Vin−), a second transistor (M3) having a gate coupled to receive a second input signal (Vin+), and a constant current source (20) coupled to sources of the first and second transistors, and providing first (4 or 6) and second (5 or 7) outputs of the differential input circuit coupled to the first (M2) and second (M3), respectively. A first slew current circuit is operated in response to the first input signal (Vin−) to produce a first slew boost current which is introduced into a current summing conductor (9) coupled to the sources of the first (M2) and second (M3) transistors and the constant current source (20).

Abstract: A differential input circuit (1) includes circuitry for generating slew boost currents to be supplied to an output stage of an operational amplifier. The differential input circuit (1) includes a differential current steering circuit including a first transistor (M2) having a gate coupled to receive a first input signal (Vin−), a second transistor (M3) having a gate coupled to receive a second input signal (Vin+), and a constant current source (20) coupled to sources of the first and second transistors, and providing first (4 or 6) and second (5 or 7) outputs of the differential input circuit coupled to the first (M2) and second (M3), respectively. A first slew current circuit is operated in response to the first input signal (Vin−) to produce a first slew boost current which is introduced into a current summing conductor (9) coupled to the sources of the first (M2) and second (M3) transistors and the constant current source (20).

Abstract: The system includes a computer (20), a detector (40) for detecting and tracking head orientation and head movement of an individual, a pair of tactile gloves (42, 44) which are donned by the individual (51) for detecting and transmitting to the computer (20) as input data orientation and movements of the hands of the individual inserted in the tactile gloves (42, 44), a stereoscopic, head-mounted display (31), a subsystem for enabling the computer to generate a stereoscopic image of the training environment, a subsystem for causing the stereoscopic image of the training environment to be displayed and changed by the computer relative to input data received by the computer relating to the head orientation and head movement of the individual, relative to input data received by the computer relating to orientation and movement of the hands of the individual inserted in the tactile gloves, and relative to input data reflecting realistic changes in the training environment that would be perceived by the individual