Abstract: The invention relates to a new method of guidance for routing of nets in an integrated circuit model wherein all nets are first approximately routed, as with Steiner routing, and victim nets with functional delay noise above predetermined thresholds are identified. Each victim net is then detail routed. For each victim net detail routed, a set of least noise aggressive neighboring nets is selected. Segments of those neighboring nets are assigned tracks adjacent to the victim net in such a way as to maximize utilization of the victim net's neighboring tracks, thereby reducing noise induced on the victim net and maximizing use of available space on the semiconductor. The process is then repeated until there are no additional victim nets, at which point the remaining nets are detail routed.

Abstract: A method and structure are provided for connecting to integrated circuitry. A connectivity cell includes multiple terminals formed within the integrated circuitry. The connectivity cell further includes at least one metal layer connected to at least one of the terminals. A first area is a substantially minimal area including the connectivity cell. A second area is a substantially minimal area including at least a part of each of multiple portions of the integrated circuitry. The portions are connectable to respective ones of the terminals while having a placement flexibility relative to the terminals. This placement flexibility of the portions is substantially equal to a placement flexibility of the second area within the first area.

Abstract: A method and apparatus for performing prenormalization during execution by an execution unit (100) of a floating-point add/subtract operation using two data operands. The execution unit (100) adds a mantissa portion of a first and a second floating-point data operand to generate a prenormalized mantissa sum. The execution unit (100) minimizes critical path delays to allow high-performance floating-point calculations while simultaneously reducing logic. Instead of treating the prenormalized mantissa sum as a 64-bit value with special treatment in case of a carry out due to overflow, the floating-point adder 100 treats the prenormalized mantissa sum as a 65-bit value, with the most significant bit being a carry output. Instead of conditionally incrementing an initial exponent value, the initial exponent value is always incremented. Thus, allowing the floating-point adder unit 100 to perform the exponent adjustments for normalization and for rounding faster.

Abstract: A data processor (10) has a floating-point execution unit (32) for executing a floating-point compare operation using two data operands. The execution unit (32) uses mantissa comparator logic (107) to perform a bit-wise comparison of a mantissa portion of a first operand with the mantissa portion of a second operand, and to provide a mantissa comparison result. Similarly, exponent comparator logic (122) performs a bit-wise comparison of an exponent portion of the first operand with the exponent portion of the second, and provides an exponent comparison result. Comparator logic (114) in the execution unit receives the mantissa comparison result and the exponent comparison result. If the exponent portions of the two operands are not equal, the comparator logic (114) uses an operand sign bit of each operand and the exponent comparison result to order the two operands.