Patents by Inventor David R. Brown

David R. Brown has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12346790
    Abstract: A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice. The state machine engine also includes a repair map buffer configured to provide repair map data to an external device via the bus interface. The state machine lattice includes multiple programmable elements. Each programmable element includes multiple memory cells configured to analyze data and to output a result of the analysis.
    Type: Grant
    Filed: February 15, 2023
    Date of Patent: July 1, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, David R. Brown
  • Publication number: 20250165265
    Abstract: A system includes a primary device comprising a first state machine lattice comprising a first plurality of configurable elements configured to analyze at least a portion of first data as a first analysis and to output a result of the first analysis.
    Type: Application
    Filed: January 16, 2025
    Publication date: May 22, 2025
    Inventors: Harold B Noyes, David R. Brown, Paul Glendenning
  • Publication number: 20250165429
    Abstract: Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 22, 2025
    Inventors: Harold B Noyes, David R. Brown
  • Publication number: 20250139011
    Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.
    Type: Application
    Filed: December 31, 2024
    Publication date: May 1, 2025
    Inventors: David R. Brown, Harold B Noyes, Inderjit Singh Bains
  • Patent number: 12223999
    Abstract: A memory device includes a command interface configured to receive write commands from a host device. The memory device also includes an input buffer configured to buffer data from the host device. The memory device further includes a write shifter configured to receive a first write command of the write commands and to shift the first command through the write shifter. The write shifter is also configured to cause the input buffer to be disabled after a first threshold of clock cycles when the first write command has shifted through the write shifter. The write shifter is additionally configured to receive a second write command and prevent the input buffer from being re-enabled until the second write command has shifted through a second threshold of stages of the write shifter.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: February 11, 2025
    Assignee: Micron Technology, Inc.
    Inventors: William Chad Waldrop, David R. Brown, Guy S. Perry, IV
  • Patent number: 12216584
    Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.
    Type: Grant
    Filed: December 4, 2023
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: David R. Brown, Harold B Noyes, Inderjit Singh Bains
  • Publication number: 20240428842
    Abstract: Apparatuses, systems, and methods for multiple types of alert along an alert bus. A memory device may detect multiple types of alert and use an alert signal along an alert bus to signal a controller of these alerts. Different pulse widths of the alert signal may be used to indicate the type of alert. For example if the alert signal is at an active level between a first duration and a second duration, it may indicate a first type of alert, if the alert signal is active between a third duration and a fourth duration, it may indicate a second type of alert. If the alert signal remains active for longer than a threshold amount of time, it may indicate a third type of alert.
    Type: Application
    Filed: June 14, 2024
    Publication date: December 26, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Yang Lu, Randall J. Rooney, David R. Brown, Michael A. Shore, Kang-Yong Kim
  • Patent number: 12130774
    Abstract: A device includes a plurality of blocks. Each block of the plurality of blocks includes a plurality of rows. Each row of the plurality of rows includes a plurality of configurable elements and a routing line, whereby each configurable element of the plurality of configurable elements includes a data analysis element comprising a plurality of memory cells, wherein the data analysis element is configured to analyze at least a portion of a data stream and to output a result of the analysis. Each configurable element of the plurality of configurable elements also includes a multiplexer configured to transmit the result to the routing line.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: October 29, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, David R. Brown, Paul Glendenning, Paul D. Dlugosch
  • Publication number: 20240355481
    Abstract: Described are systems and methods configured to accurately identify risk levels for individuals with varying sensitivities for those in close proximity to an emitting source and illustrates the impact of weather on levels of toxic concentration of airborne chemicals. As the methods and implementations described herein can be used for any location and any polluting point source of airborne chemicals, it can be a valuable tool to help residents in their efforts to reduce exposures and for medical providers to more accurately diagnose and treat exposed patients. For various distances from a polluting source, this methodology integrates weather, air dispersion analysis and emissions data of a single chemical or mixture of chemicals to provide a quantitative estimate of the frequency of unhealthy exposures to airborne toxins. Moreover, it specifies the frequency and past hours of unhealthy exposures according to the exposed person's sensitivity level.
    Type: Application
    Filed: April 13, 2024
    Publication date: October 24, 2024
    Inventors: Amy Rosmarin, David R. Brown
  • Patent number: 12096989
    Abstract: A system and method for performing a procedure is disclosed. The procedure may include preparing one or more bones for a prosthetic implant. The method may include provide instructions to a user for using identified instruments to perform a procedure. Instructions and may be provided for settings of adjustable instruments.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: September 24, 2024
    Assignee: Biomet Manufacturing, LLC
    Inventors: David R. Brown, Troy W. Hershberger
  • Publication number: 20240241736
    Abstract: A system includes a primary device comprising a first state machine lattice comprising a first plurality of configurable elements configured to analyze at least a portion of first data as a first analysis and to output a result of the first analysis.
    Type: Application
    Filed: March 29, 2024
    Publication date: July 18, 2024
    Inventors: Harold B Noyes, David R. Brown, Paul Glendenning
  • Patent number: 12019512
    Abstract: A memory device includes a command interface that when operating receives a write command, an input output interface that when in operation receives data signals in conjunction with the write command, and error detection circuitry coupled to the input output interface. The error detection circuitry is configured to generate a first signal indicative of a first period of time during which a first determination is made regarding a first portion of the data signals utilizing a first data strobe signal as a first clock signal, generate a second signal indicative of a second period of time during which a second determination is made regarding a second portion of the data signals utilizing a second data strobe signal as a second clock signal, and generate a control signal based upon the first signal, the second signal, and a slower of the first data strobe signal and the second data strobe signal.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: June 25, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Thanh K. Mai, Parthasarathy Gajapathy, David R. Brown
  • Publication number: 20240194239
    Abstract: Methods, apparatuses, and systems related to managing operations performed in response to refresh management (RFM) commands. A controller generates the RFM command for coordinating a refresh management operation targeted for implementation at an apparatus. The apparatus tracks refresh target set that includes refresh management target locations within the apparatus. According to the tracked refresh management target set, the apparatus selectively implements the targeted refresh management operation and/or a response operation in addition to or as a replacement for the targeted refresh management operation.
    Type: Application
    Filed: February 21, 2024
    Publication date: June 13, 2024
    Inventors: Nathaniel J. Meier, James S. Rehmeyer, David R. Brown
  • Patent number: 11977977
    Abstract: A device includes a match element that includes a first data input configured to receive a first result, wherein the first result is of an analysis performed on at least a portion of a data stream by an element of a state machine. The match element also includes a second data input configured to receive a second result, wherein the second result is of an analysis performed on at least a portion of the data stream by another element of the state machine. The match element further includes an output configured to selectively provide the first result or the second result.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: May 7, 2024
    Assignee: Micron Technology, Inc.
    Inventors: David R. Brown, Harold B Noyes
  • Patent number: 11947979
    Abstract: A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: April 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, David R. Brown, Paul Glendenning
  • Publication number: 20240104020
    Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.
    Type: Application
    Filed: December 4, 2023
    Publication date: March 28, 2024
    Inventors: David R. Brown, Harold B. Noyes, Inderjit Singh Bains
  • Patent number: 11915737
    Abstract: Methods, apparatuses, and systems related to managing operations performed in response to refresh management (RFM) commands A controller generates the RFM command for coordinating a refresh management operation targeted for implementation at an apparatus. The apparatus tracks refresh target set that includes refresh management target locations within the apparatus. According to the tracked refresh management target set, the apparatus selectively implements the targeted refresh management operation and/or a response operation in addition to or as a replacement for the targeted refresh management operation.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: February 27, 2024
    Inventors: Nathaniel J. Meier, James S. Rehmeyer, David R. Brown
  • Publication number: 20240012787
    Abstract: Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix.
    Type: Application
    Filed: September 22, 2023
    Publication date: January 11, 2024
    Inventors: Harold B. Noyes, David R. Brown
  • Publication number: 20240005980
    Abstract: A memory device includes a command interface configured to receive write commands from a host device. The memory device also includes an input buffer configured to buffer data from the host device. The memory device further includes a write shifter configured to receive a first write command of the write commands and to shift the first command through the write shifter. The write shifter is also configured to cause the input buffer to be disabled after a first threshold of clock cycles when the first write command has shifted through the write shifter. The write shifter is additionally configured to receive a second write command and prevent the input buffer from being re-enabled until the second write command has shifted through a second threshold of stages of the write shifter.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Inventors: William Chad Waldrop, David R. Brown, Guy S. Perry, IV
  • Publication number: 20230393929
    Abstract: A memory device includes a command interface that when operating receives a write command, an input output interface that when in operation receives data signals in conjunction with the write command, and error detection circuitry coupled to the input output interface. The error detection circuitry is configured to generate a first signal indicative of a first period of time during which a first determination is made regarding a first portion of the data signals utilizing a first data strobe signal as a first clock signal, generate a second signal indicative of a second period of time during which a second determination is made regarding a second portion of the data signals utilizing a second data strobe signal as a second clock signal, and generate a control signal based upon the first signal, the second signal, and a slower of the first data strobe signal and the second data strobe signal.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: Thanh K. Mai, Parthasarathy Gajapathy, David R. Brown