Abstract: An occupant position and weight estimation apparatus includes an elastomeric seat bladder having physically isolated central and peripheral fluid-filled chambers corresponding to central and peripheral areas of the seat. The fluid pressure in the peripheral chamber is primarily activated by a child or infant seat, whereas the fluid pressure in the central chamber is primarily activated by a normally seated occupant. The chambers have extensions or fingers that are interdigitated so that shifting of a normally seated occupant from the central area of the seat to a peripheral region of the seat is easily detected based on changes in the relative fluid pressures in the central and peripheral chambers. An extension of the peripheral chamber at the middle forward portion of the seat that is not engaged by a normally seated occupant can also be used to detect an out-of-position occupant in close proximity to a frontal air bag.

Abstract: A digital hearing aid is provided that includes front and rear microphones, a sound processor, and a speaker. Embodiments of the digital hearing aid include an occlusion subsystem, and a directional processor and headroom expander. The front microphone receives a front microphone acoustical signal and generates a front microphone analog signal. The rear microphone receives a rear microphone acoustical signal and generates a rear microphone analog signal. The front and rear microphone analog signals are converted into the digital domain, and at least the front microphone signal is coupled to the sound processor. The sound processor selectively modifies the signal characteristics and generates a processed signal. The processed signal is coupled to the speaker which converts the signal to an acoustical hearing aid output signal that is directed into the ear canal of the digital hearing aid user.

Abstract: A digital hearing aid is provided that includes front and rear microphones, a sound processor, and a speaker. Embodiments of the digital hearing aid include an occlusion subsystem, and a directional processor and headroom expander. The front microphone receives a front microphone acoustical signal and generates a front microphone analog signal. The rear microphone receives a rear microphone acoustical signal and generates a rear microphone analog signal. The front and rear microphone analog signals are converted into the digital domain, and at least the front microphone signal is coupled to the sound processor. The sound processor selectively modifies the signal characteristics and generates a processed signal. The processed signal is coupled to the speaker which converts the signal to an acoustical hearing aid output signal that is directed into the ear canal of the digital hearing aid user.

Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

Abstract: An apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. Each time value from the set of time values is uniquely associated with a detected edge transition from the input signal. The memory is coupled to the edge detector. The memory is configured to receive from the edge detector the set of time values. The memory is configured to store the set of time values. The pulse-input engine is coupled to the memory. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of the time values stored in the memory.

Abstract: A phase splitter is formed by first and second branches that generate respective first and second complimentary output clock signals from an input clock signal. The first branch includes two series connected inverters, the first of which receives the input clock signal and the second of which outputs a non-complimentary output clock signal. The second branch includes three series connected inverters, the first of which receives the input clock signal and the third of which outputs a complimentary output clock signal. An inverter is coupled from the output of the second inverter in the second branch to the output of the first inverter in the first branch to increase the slew rate of the signal applied to the input of the second inverter. In one embodiment, first and second parallel pairs of diode-coupled transistors are coupled from the output of the third inverter in the second branch to the outputs of respective first inverters in the first and second branches.

Abstract: An apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. Each time value from the set of time values is uniquely associated with a detected edge transition from the input signal. The memory is coupled to the edge detector. The memory is configured to receive from the edge detector the set of time values. The memory is configured to store the set of time values. The pulse-input engine is coupled to the memory. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of time values stored in the memory.

Abstract: A method and a mask have been optimized to reduce seam lines in replicated structures using lithographic processes. Multiple exposures and sweeps across a substrate using the mask results in the reduction of seam lines in the final developed photosensitive or micro formed structures.

Abstract: Methods and apparatuses for minimizing the errors associated with substrate etching are presented. The methods and apparatuses use intentional defocusing of the pattern image on the photoresist to minimize errors in the etching process particularly grayscale etching and multiple exposure contributions from neighboring patterns.

Abstract: A semiconductor memory device is organized in such a way that undesirable interference and cross-coupling between various signals generated during operation of the device is minimized. The semiconductor memory device comprises an array of rows and columns of memory cells organized logically and physically into a plurality of sub-arrays. Within each sub-array, the memory cells are organized logically and physically into a plurality of dependent, interleaved banks of memory cells. The banks of memory cells, in turn, each comprise a plurality of memory cores comprising a plurality of memory cells. The memory cores are arranged in such a way as to define a plurality of substantially elongate, orthogonal “stripes” therebetween. Row decoder circuitry for selecting a specified row of memory cells is disposed along the stripes extending in a first direction.

Abstract: A mechanism for optimizing transaction retries within a system utilizing a peripheral component interconnect (PCI) bus architecture. Specifically, one embodiment of the present invention includes a system which optimizes transaction retries issued by a PCI bus master device to a target device coupled to a PCI bus. The system includes a target device communicatively coupled to a PCI bus and able to issue a retry signal over the PCI bus. Furthermore, the system includes a PCI bus master device communicatively coupled to the PCI bus and able to issue a transaction signal to the target device over the PCI bus. Moreover, the system includes a retry timer circuit coupled to the PCI bus master device in order to respond when the PCI bus master device receives the retry signal issued by the target device over the PCI bus. The retry timer circuit causes the PCI bus master device to wait a fixed period of time before reissuing the transaction signal to the target device over the PCI bus.

Abstract: A measurement system and method for determining a revolution rate of a rotating gear is described. Such a rotating gear can be, for example, a turbine or compressor. The described measurement system and method, for example, can perform highly accurate measurements and can be a fault tolerant system providing high reliability. In one embodiment, an apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of time values stored in the memory.

Abstract: Embodiments of the invention provide methods and processes for creating and using high precision molds for creating micro-optical elements, such as micro-lenses. A master mold is created using one of at least gray scale technologies or direct write lithography to provide highly accurate micro-optical contours on a substrate or resist layer upon which the master mold is formed. The master mold may be used to create secondary molds for use in production of highly precise micro-optical elements from various materials.

Abstract: An apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. Each time value from the set of time values is uniquely associated with a detected edge transition from the input signal. The memory is coupled to the edge detector. The memory is configured to receive from the edge detector the set of time values. The memory is configured to store the set of time values. The pulse-input engine is coupled to the memory. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of time values stored in the memory.

Abstract: A photolithographic process includes providing a layer of photoresistive material on a target substrate. Radiation is transmitted to the photoresistive material through a layer of absorbing material that absorbs the radiation with a transmittance proportional to the thickness of the absorbing material. A surface relief structure is formed in the absorbing material, so that the photoresistive material is only partially exposed in a pattern corresponding to the surface relief structure. Thus, when the photoresistive material is developed, it has a surface relief structure corresponding to the surface relief structure in the absorbing material. Etching the developed photoresistive material and target substrate then forms a surface relief structure in the target substrate that corresponds to the surface relief structure in the developed photoresistive material.

Abstract: A method and corresponding architecture are disclosed for sharing redundant rows between banks of a memory array. The architecture is such that sub-arrays associated with different banks are alternated and coupled via a sense amp. In addition, sub-arrays belonging to the same bank are coupled via a single row decoder. This architecture allows for adjacent sub-arrays belonging to different banks to share redundant rows, thereby effectively doubling the number of redundant rows available for use in a given bank.

Abstract: An improved architecture for a semiconductor memory device. In one embodiment, a semiconductor memory device is organized in such a way that undesirable interference and cross-coupling between various signals generated during operation of the device is minimized. The semiconductor memory device comprises an array of rows and columns of memory cells organized logically and physically into a plurality of sub-arrays. Within each sub-array, the memory cells are organized logically and physically into a plurality of dependent, interleaved banks of memory cells. The banks of memory cells, in turn, each comprise a plurality of memory cores comprising a plurality of memory cells. The memory cores are arranged in such a way as to define a plurality of substantially elongate, orthogonal “stripes” therebetween. Row decoder circuitry for selecting a specified row of memory cells is disposed along the stripes extending in a first direction.

Abstract: A digital hearing aid is provided that includes front and rear microphones, a sound processor, and a speaker. Embodiments of the digital hearing aid include an occlusion subsystem, and a directional processor and headroom expander. The front microphone receives a front microphone acoustical signal and generates a front microphone analog signal. The rear microphone receives a rear microphone acoustical signal and generates a rear microphone analog signal. The front and rear microphone analog signals are converted into the digital domain, and at least the front microphone signal is coupled to the sound processor. The sound processor selectively modifies the signal characteristics and generates a processed signal. The processed signal is coupled to the speaker which converts the signal to an acoustical hearing aid output signal that is directed into the ear canal of the digital hearing aid user.