Abstract: A processing system includes memory page selection of multiple memory pages in an interrupt environment. The processing system includes a processor and memory page selection control for selecting one memory page responsive to a first address generated by the processor and another memory page responsive to a second address generated by the processor. The memory page selection control includes a page latch which can be overridden by an interrupt to permit the processor to service an interrupt from one of the pages but which returns the processor to the memory page from which it was fetching program instructions at the time of the interrupt. To coordinate page selection, the processor executes program instructions from dedicated paging instructions including interface modules, decode modules, and transition modules stored in each page which are configured to assure smooth page transitions and efficient interrupt servicing.