Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Abstract: A system includes a plurality of processors, each being coupled to each of remaining processors via a cluster of processor interconnects. The cluster of processor interconnects form a data distribution network. The system further includes a plurality of roots coupled to the processors, each root corresponding to one of the processors. Each root comprises a memory controller, one or more branches coupled to the memory controller, and a plurality of memory leaves coupled to the branches, each memory leaf having one or more solid state memory devices. Each of the branches is associated with one or more of the memory leaves and provides access to the associated memory leaves. Each of the processors can access any one of the memory leaves via a corresponding branch of any one of the roots over the data distribution network.

Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Abstract: A system includes a plurality of processors, each being coupled to each of remaining processors via a cluster of processor interconnects. The cluster of processor interconnects form a data distribution network. The system further includes a plurality of roots coupled to the processors, each root corresponding to one of the processors. Each root comprises a memory controller, one or more branches coupled to the memory controller, and a plurality of memory leaves coupled to the branches, each memory leaf having one or more solid state memory devices. Each of the branches is associated with one or more of the memory leaves and provides access to the associated memory leaves. Each of the processors can access any one of the memory leaves via a corresponding branch of any one of the roots over the data distribution network.

Abstract: A system includes a collection of central processing units, where each central processing unit is connected to at least one other central processing unit and a root path into at least 10 Tera Bytes of solid state memory resources. Each central processing unit directly accesses solid state memory resources without swapping solid state memory contents into main memory.

Abstract: A secondary controller for controlling the performance of a vehicle is described. The secondary controller sends control commands to a vehicle controller while the vehicle is being driven to effect the operation of the vehicle's power train without requiring any modification of the vehicle controller and without falsifying any information sent to the vehicle controller. In some embodiments, the secondary controller communicates with the vehicle controller via the vehicle's diagnostic port, such as an OBD-II port. In one aspect, the secondary controller is used to direct the vehicle controller not to utilize a start/stop feature to automatically turn off the engine in the selected circumstances during normal operation of the vehicle. As such, the control command causes the vehicle controller to operate the vehicle in the selected operating mode in manner dictated by the engine controller.

Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Abstract: A secondary controller for controlling the performance of a vehicle is described. The secondary controller sends control commands to a vehicle controller while the vehicle is being driven to effect the operation of the vehicle's power train without requiring any modification of the vehicle controller and without falsifying any information sent to the vehicle controller. In some embodiments, the secondary controller communicates with the vehicle controller via the vehicle's diagnostic port, such as an OBD-II port. In one aspect, the secondary controller is used to direct the vehicle controller not to utilize a start/stop feature to automatically turn off the engine in the selected circumstances during normal operation of the vehicle. As such, the control command causes the vehicle controller to operate the vehicle in the selected operating mode in manner dictated by the engine controller.

Abstract: A secondary controller for controlling the performance of a moving automobile is described. The secondary controller can be configured to communicate with one or more vehicle controllers, such as the engine control unit, while the automobile is being driven. The secondary controller can send control commands, such as self-test or diagnostic commands to the vehicle controller to effect the operation of the vehicle's power train. The secondary controller can receive power train related data from the engine control unit and based upon the received power train data determine when to send the control commands. In one embodiment, the secondary controller communicates with the vehicle controller via the vehicle's diagnostic port, such as an OBD-II port. In another embodiment, the secondary controller can be configured to control a variable displacement engine in a vehicle to improve the fuel efficiency of the vehicle while it is driven.

Abstract: A secondary controller for controlling the performance of a moving automobile is described. The secondary controller can be configured to communicate with one or more vehicle controllers, such as the engine control unit, while the automobile is being driven. The secondary controller can send control commands to the vehicle controller to effect the operation of the vehicle's power train. The secondary controller can receive power train related data from the engine control unit and based upon the received power train data determine when to send the control commands. In one embodiment, the secondary controller communicates with the vehicle controller via the vehicle's diagnostic port, such as an OBD-II port. In another embodiment, the secondary controller can be configured to control the operational displacement of a variable displacement engine while the vehicle is driven.

Abstract: A secondary controller for controlling the performance of a moving automobile is described. The secondary controller can be configured to communicate with one or more vehicle controllers, such as the engine control unit, while the automobile is being driven. The secondary controller can send control commands to the vehicle controller to effect the operation of the vehicle's power train. The secondary controller can receive power train related data from the engine control unit and based upon the received power train data determine when to send the control commands. In one embodiment, the secondary controller communicates with the vehicle controller via the vehicle's diagnostic port, such as an OBD-II port. In another embodiment, the secondary controller can be configured to control the operational displacement of a variable displacement engine while the vehicle is driven.

Abstract: A secondary controller for controlling the performance of a moving automobile is described. The secondary controller can be configured to communicate with one or more vehicle controllers, such as the engine control unit, while the automobile is being driven. The secondary controller can send control commands, such as self-test or diagnostic commands to the vehicle controller to effect the operation of the vehicle's power train. The secondary controller can receive power train related data from the engine control unit and based upon the received power train data determine when to send the control commands. In one embodiment, the secondary controller communicates with the vehicle controller via the vehicle's diagnostic port, such as an OBD-II port. In another embodiment, the secondary controller can be configured to control a variable displacement engine in a vehicle to improve the fuel efficiency of the vehicle while it is driven.

Abstract: A method of providing ad hoc verification for a simulation includes generating a cumulative record of a state value for the simulation of a circuit design, comparing the cumulative record of the state value to a golden record of the state value to obtain a comparison result, and performing ad hoc verification of the circuit design using the comparison result.

Abstract: A method of providing accelerated post-silicon testing for a silicon hardware includes computing a simulation cumulative record of state using a plurality of test instructions and a cycle breakpoint, performing a simulation of an instrumented logic design using the plurality of test instructions and the cycle breakpoint, manufacturing the silicon hardware using the instrumented logic design, computing a silicon cumulative record of state by executing the plurality of instructions using the silicon hardware; and comparing the simulation cumulative record of state to the silicon cumulative record of state.

Abstract: According to the invention, a processing core (12) comprising a processing pipeline (100) having N-number of processing paths (56), each of which process instructions (54) on M-bit data words. In addition, the processing core (12) includes one or more register files (60), each preferably having Q-number of registers which are M-bits wide. Preferably, one of the Q-number of registers in at least one of the register files (60) is a program counter register dedicated to hold a program counter, and one of the Q-number of registers in at least one of the register files is a zero register dedicated to hold a zero value. In this manner, program jumps can be executed by adding values to the program counter in the program counter register, and memory address values can be calculated by adding values to the program counter stored in the program counter register or to the zero value stored in the zero register.

Abstract: A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first sub-cluster crossbar is connected to a first plurality of execution processors. A second sub-cluster crossbar is associated with a second one of the plurality of statically scheduled routing processors where the second sub-cluster crossbar is connected to a second plurality of execution processors.

Abstract: A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.

Abstract: A method for performing debugging of an executable source program in a massively parallel processing environment involves associating a major cycle counter and a minor cycle counter with each of a plurality of execution processors in the massively parallel processing environment, obtaining a first stopping point value associated with the major cycle counter and a second stopping point value associated with the minor cycle counter, executing instructions of the executable source program on each of the plurality of execution processors, modifying the major cycle counter and the minor cycle counter, and halting each of the plurality of execution processors and returning control to the user if the major cycle counter reaches the first stopping point value and the minor cycle counter reaches the second stopping point value.

Abstract: A method for controlling a processor array by a host computer involves creating a graph of a plurality of nodes using a data connection component, configuring a broadcast tree from a spanning tree of the graph, propagating a first command from the host computer to a member of the processor array using the broadcast tree, configuring a reply tree from a spanning tree of the graph, transmitting a response from the member of the processor array to the host computer using the reply tree, and configuring the data connection component to send at least one message selected from the first command and the response on at least one run mode communication path.