Abstract: The present invention relates to a system and method for reducing the power consumption of a computer system, more specifically a notebook computer system. The system comprises a programmable frequency generator and a programmable power supply which alters the current operating frequency and voltage of the computer's microprocessor to match current operating conditions. If the microprocessor is not doing any meaningful work, the programmable frequency generator and the programmable power supply can reduce both the operating frequency and voltage thereby lowering the power consumption of the computer system based on the formula: power=voltage.sup.2 .times.frequency. It should be noted that the programmable frequency generator and the programmable power supply may be attached to other system components in the computer system that consume a large amount of the computer system's power.

Abstract: The present invention relates to a system and method for implementing peripheral device bus mastering in a mobile computer system. The system uses the mobile computer system's microcontroller for programming a DMA controller, generating and sending command signals, and receiving completion status after transfer of data is complete. The micro-controller accesses a data buffer descriptor list. The data buffer descriptor list describes each data transfer that the micro-controller initiates, controls, and completes. The Direct Memory Access controller which is programmed by the micro-controller transfers data to and from a memory section of the mobile computer system. A bus controller is used for implementing a memory data transfer request from the DMA controller means and the micro-controller means.

Abstract: The present invention is a system and method for implementing peripheral device bus mastering in a mobile computer system. The system uses the micro-controller of the mobile computer system to program a DMA controller. The DMA controller transfers data to and from the memory of the mobile computer system. A bus controller which is coupled to both the micro-controller and the DMA controller implements a memory data transfer request from the DMA controller and the micro-controller. A device controller, either a IDE hard disk controller or an ECP parallel port controller, is also coupled to the DMA controller and the micro-controller. The device controller receives and responds to the command signals from the micro-controller by transferring data to and from the DMA controller means and generating a completion signal when the transfer is complete.

Abstract: The present invention relates to a system and method for dynamically altering the speed of a bus based on utilization of the bus. The system will monitor a bus for a predetermined number of clock cycles. The system will then lower the frequency that the bus runs at if the bus is underutilized, or the system will increase the frequency that the bus runs at if the bus is at or nearing saturation.

Abstract: The present invention relates to a system and method for passing Industry Standard Architecture (ISA) legacy interrupts across Peripheral Component Interconnect (PCI) connectors. The system interconnects a plurality of PCI devices coupled to a PCI bus such that a last interrupt pin of each of the plurality of PCI devices are coupled together in a directly bussed manner to provide a serial interrupt signal line. The remainder of the interrupt pins of each of the plurality of PCI devices are coupled together in a barber pole manner.

Abstract: An I/O holdoff mechanism is used to compensate for I/O device inputs being fed through a latency introducing bus. A system includes one or more I/O devices connected through a serial bus to a controller device. Each I/O device includes at least one request pin which is connected to a peripheral device. A serializer in the I/O device responds to a voltage transition occurring on any request pin of the I/O device by forwarding, in a packet over the serial bus, an indicator. The indicator indicates a current voltage on the request pin of the I/O device on which the voltage transition occurred. The controller device includes a deserializer and a bus controller. The deserializer receives the first packet and outputs a signal which indicates a current value for the voltage on the indicated request pin. The deserializer includes a busy output which indicates when the deserializer is busy and when the deserializer is idle.

Abstract: A PLL based microprocessor whose frequency may be adjusted by using a microprocessor clock control circuit. The microprocessor clock control circuit comprises a circuit for providing a slew rate limited overdampened PLL that continuously seeks a new frequency, a circuit for selecting a current target frequency for the microprocessor, a circuit for comparing the current target frequency to the current frequency setting of the microprocessor, and a circuit for adjusting the current frequency setting of the microprocessor to match the current target frequency.

Abstract: A computing system encodes and emulates requests signals, such as DMA requests or interrupt requests. A first peripheral device is connected to a first request pin of a first input/output (I/O) device. When the first peripheral device asserts a first request signal on the first request pin, a serializer within the first I/O device generates a first packet. The serializer forwards the first packet to a serial out port of the first I/O device. The first packet identifies the type of request and the direction of the edge transition. The serial out port forwards the first packet to a serial in port of a controller device. Upon the serial in port receiving the first packet, an unserializer within the controller device asserts an emulated first request signal, the emulated first request signal being coupled to a first request controller within the controller device.

Abstract: A distributed I/O device monitoring logic for power management control. The distributed I/O device monitoring logic reduces the gate count of convention device monitoring logic since the decode logic does not exist at two locations in the system. The distributed I/O device monitoring logic also has the benefits of self configuring monitor circuits, improved functionality, and decreased system power management overhead. The distributed I/O device monitoring logic comprises peripheral control for monitoring an I/O address range of at least one I/O device and for detecting access to the I/O device; system controller means coupled to the peripheral control for providing a ready (RDY #) signal and a system management interrupt (SMI #) signal; and central processing unit (CPU) coupled to the peripheral control and the system controller means for receiving the RDY # signal and the SMI # signal from the system controller and for sending information to both the system controller and the peripheral control.

Abstract: A shared keyboard and system ROM uses a single ROM for both the keyboard and the system operating system information (BIOS). The shared ROM is never simultaneously used for both of these functions. At initial boot-up, the system processor executes from the shared ROM to copy the system BIOS information to the system Random Access Memory DRAM. Once this copying has been completed, the shared ROM then is used by the keyboard subsystem. Different address ranges are employed in the shared ROM for the keyboard information and for the system BIOS.

Abstract: A Central Processing Unit (CPU) debugging device and method therefor is disclosed which provides data entering and interrogating devices which will temporarily stop all CPU execution when desired by a user and allow a non-destructive intrusion into the contents of any of the CPU internal registers, state bits, and cache and local memories. After the desired CPU contents have been reviewed and subsequently altered or maintained by a user, the CPU execution may be resumed.

Abstract: A serial bus Input/Output (I/O) system has multiple I/O devices which are all connected in daisy-chain fashion on a serial bus. These I/O devices service peripherals that may generate different interrupt requests or DMA requests to the system controller. These requests are encoded, serialized and transmitted to the system controller on the serial bus, allowing the system controller to service a large number of interrupt requests and DMA requests via the serial bus with a very small number of external pins.

Abstract: An electronic system has multiple identical Input/Output (I/O) devices which are all connected in daisy-chain fashion on a serial bus. At power-up or reset, the I/O device at the end of the chain configures itself as Device 0, and outputs data to the next device which configures it as Device 1. Device 1 then outputs data to the next device which configures it as Device 2, and so on until all the I/O devices have been assigned a device number. In this manner the I/O devices are configured to unique addresses without additional external pins or intervention by the System Controller, minimizing package size and eliminating logic which would otherwise be required if the System Controller had to configure these I/O devices.