Patents by Inventor David R. Follett
David R. Follett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10303697Abstract: A method for processing data is provided. Data is identified by a computer system. The data is processed in parallel by the computer system using temporal transformations to form pieces of temporal data. The pieces of temporal data are placed by the computer system in an order as the pieces of temporal data are generated by the temporal transformations to form a sequence of temporal data. The order of the sequence is based on a priority of when the pieces of temporal data should be processed, enabling performing an action.Type: GrantFiled: June 25, 2015Date of Patent: May 28, 2019Assignees: National Technology & Engineering Solutions of Sandia, LLC, Lewis Rhodes Labs, Inc.Inventors: John H. Naegle, James Bradley Aimone, Frances S. Chance, Craig Michael Vineyard, David R. Follett, Pamela L. Follett
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Patent number: 7295557Abstract: A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network.Type: GrantFiled: May 7, 2004Date of Patent: November 13, 2007Assignee: Emulex Design & Manufacturing CorporationInventors: Shawn A. Clayton, David R. Follett, Nitin D. Godiwala, Maria C. Gutierrez, David S. Wells, James B. Williams
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Patent number: 7283471Abstract: A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network.Type: GrantFiled: March 11, 2003Date of Patent: October 16, 2007Assignee: Emulex Design & Manufacturing CorporationInventors: Maria C. Gutierrez, Shawn Adam Clayton, David R. Follett, Harold E. Roman, Nitin D. Godiwala, Richard F. Prohaska, James B. Williams
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Publication number: 20040208181Abstract: A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network.Type: ApplicationFiled: May 7, 2004Publication date: October 21, 2004Applicant: Emulex Design & Manufacturing CorporationInventors: Shawn A. Clayton, David R. Follett, Nitin D. Godiwala, Maria C. Gutierrez, David S. Wells, James B. Williams
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Patent number: 6795442Abstract: A system includes interconnected computers and switching nodes. A source computer for the virtual circuits schedules message transmissions on a round-robin basis. Each switching node also forwards messages in a round-robin manner, and a destination computer schedules processing of received messages in a round-robin manner. In addition, messages are transmitted in cells to reduce delays in short messages if long messages are transmitted for one virtual circuit before transmission of a short message for another virtual circuit. For each virtual circuit, the destination computer and each switching node can generate a virtual circuit flow control message to temporarily limit transmissions if the resources being taken up by messages exceed predetermined thresholds. In addition, each switching node or computer can generate link flow control messages for transmission to neighboring devices to temporarily limit transmissions if the resources taken up by all virtual circuits exceeds predetermined thresholds.Type: GrantFiled: April 23, 1998Date of Patent: September 21, 2004Assignee: Emulex Design & Manufacturing CorporationInventors: Shawn A. Clayton, David R. Follett, Nitin D. Godiwala, Maria C. Gutierrez, David S. Wells, James B. Williams
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Publication number: 20030174647Abstract: A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network.Type: ApplicationFiled: March 11, 2003Publication date: September 18, 2003Applicant: Emulex Corporation, a California corporationInventors: Maria C. Gutierrez, Shawn A. Clayton, David R. Follett, Nitin D. Godiwala, Richard F. Prohaska, Harold E. Roman, James B. Williams
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Patent number: 6570850Abstract: A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network.Type: GrantFiled: April 23, 1998Date of Patent: May 27, 2003Assignee: Giganet, Inc.Inventors: Maria C. Gutierrez, Shawn A. Clayton, David R. Follett, Nitin D. Godiwala, Richard F. Prohaska, Harold E. Roman, James B. Williams
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Patent number: 6094712Abstract: A computer interface system for communicating between computers along designated circuits is provided. An interface unit is provided in each host computer. Each unit includes a memory map that stores a map of physical addresses that correspond to virtual addresses for each application involved in a communication link. Each transfer of data is designated by a circuit that is established using the ATM protocol. The circuit is recognized by each unit involved in the communication and facilitates direct access of each host computer's main memory with minimum intervention from the operating system. A novel dynamic buffer management system is also provided.Type: GrantFiled: December 4, 1996Date of Patent: July 25, 2000Assignee: Giganet, Inc.Inventors: David R. Follett, Maria C. Gutierrez, Richard F. Prohaska
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Patent number: 5426639Abstract: The operation of a packet switch having a plurality of port circuits is enhanced by including in a port circuit a virtual FIFO for each source of data packets that the port circuit serves, such that the storage capacity of a FIFO increases and decreases as required by the associated source.Type: GrantFiled: November 29, 1991Date of Patent: June 20, 1995Assignee: AT&T Corp.Inventors: David R. Follett, Carol A. Tourgee
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Patent number: 4872163Abstract: A contention mechanism is disclosed for a communication network that provides perfect scheduling to avoid collisions between packets from a cluster of M circuit boards connected to a communications bus. The contention mechanism includes a 2-phase contention procedure comprising a first phase priority contention phase, where boards with a highest priority and a real data packet to transmit proceed into a second contention phase, where a pointer is used to declare one of the remaining priority phase circuit boards as the overall winner to transmit its packet during a subsequent packet period. When no circuit board has a packet to transmit, all M circuit boards are declared as winners of the first priority phase, and a board is declared the winner on a distributed basis to transmit a "dead-space" packet over the bus.Type: GrantFiled: December 22, 1988Date of Patent: October 3, 1989Assignees: American Telephone and Telegraph Company, AT&T Bell LaboratoriesInventors: David R. Follett, Michael P. Levy
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Patent number: 4870637Abstract: The present invention relates to an optical backplane for use in a switching system or computer for interconnecting a plurality of associated circuit modules. The backplane comprises a switch which is interconnected to each of the associated circuit modules by a separate multifiber ribbon, each ribbon including (1) a plurality of transmit and receive optical fibers, and (2) an optical fiber for providing concurrent synchronization signals to each of the associated circuit modules. The switch includes a switching block for coupling parallel optical signals received from the plurality of receive optical fibers in any multifiber ribbon, transmitted by a sending module, to the transmit fibers of each of the multifiber ribbons for transmission to all of the modules associated with the optical backplane.Type: GrantFiled: December 24, 1987Date of Patent: September 26, 1989Assignees: American Telephone and Telegraph Company, AT&T Bell LaboratoriesInventors: David R. Follett, David L. Sobin
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Patent number: 4568982Abstract: Disclosed is a high resolution optical scanning method and apparatus. Light from a source, such as a laser, is focused onto a flat, rotating mirror. The reflected light is made incident upon a stationary elliptical mirror such that the real or virtual source is at one focus of the ellipse and the points on the line to be scanned are at the other focus along the lateral dimension of the mirror. A large useful angle of rotation is thereby achieved for each line scan.Type: GrantFiled: April 9, 1984Date of Patent: February 4, 1986Assignee: AT&T LaboratoriesInventor: David R. Follett