Patents by Inventor David R. Gifford
David R. Gifford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11853683Abstract: Systems and methods related to learning-based analyzers (both supervised and unsupervised) for mitigating latch-up in integrated circuits are provided. An example method includes obtaining latch-up data concerning at least one integrated circuit configured to operate under a range of temperature conditions, where the at least one integrated circuit comprises a core portion including at least a plurality of devices each having one or more structural features formed using a lithographic process, and an input/output portion. The method further includes training the learning-based system based on training data derived from the latch-up data and a first layout rule concerning a first spacing between the core portion and the input/output portion. The method further includes using the learning-based system generating a second layout rule concerning the first spacing between the core portion and the input/output portion, where the second layout rule is different from the first layout rule.Type: GrantFiled: October 3, 2022Date of Patent: December 26, 2023Assignee: Silicon Space Technology CorporationInventors: Patrice M. Parris, David R. Gifford, Bernd Lienhard
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Publication number: 20230088804Abstract: Systems and methods related to learning-based analyzers (both supervised and unsupervised) for mitigating latch-up in integrated circuits are provided. An example method includes obtaining latch-up data concerning at least one integrated circuit configured to operate under a range of temperature conditions, where the at least one integrated circuit comprises a core portion including at least a plurality of devices each having one or more structural features formed using a lithographic process, and an input/output portion. The method further includes training the learning-based system based on training data derived from the latch-up data and a first layout rule concerning a first spacing between the core portion and the input/output portion. The method further includes using the learning-based system generating a second layout rule concerning the first spacing between the core portion and the input/output portion, where the second layout rule is different from the first layout rule.Type: ApplicationFiled: October 3, 2022Publication date: March 23, 2023Inventors: Patrice M. Parris, David R. Gifford, Bernd Lienhard
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Patent number: 11587822Abstract: Structures and processes for improving radiation hardness and eliminating latch-up in integrated circuits are provided. An example process includes forming a first doped buried layer, a first well, and a second well, and using a first mask, forming a second doped buried layer only in a first region above the first doped buried layer and between at least the first well and the second well, where the first mask is configured to control spacing between the wells and the doped buried layers. The process further includes using a second mask, forming a vertical conductor located only in a second region above the first region and between at least the first well and the second well, where the vertical conductor is doped to provide a low resistance link between the second doped buried layer and at least a top surface of the substrate.Type: GrantFiled: October 28, 2020Date of Patent: February 21, 2023Assignee: Silicon Space Technology CorporationInventors: David R. Gifford, Patrice M. Parris
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Patent number: 11461531Abstract: Systems and methods related to learning-based analyzers (both supervised and unsupervised) for mitigating latch-up in integrated circuits are provided. An example method includes obtaining latch-up data concerning at least one integrated circuit configured to operate under a range of temperature conditions, where the at least one integrated circuit comprises a core portion including at least a plurality of devices each having one or more structural features formed using a lithographic process, and an input/output portion. The method further includes training the learning-based system based on training data derived from the latch-up data and a first layout rule concerning a first spacing between the core portion and the input/output portion. The method further includes using the learning-based system generating a second layout rule concerning the first spacing between the core portion and the input/output portion, where the second layout rule is different from the first layout rule.Type: GrantFiled: April 29, 2019Date of Patent: October 4, 2022Assignee: Silicon Space Technology CorporationInventors: Patrice M. Parris, David R. Gifford, Bernd Lienhard
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Publication number: 20210043496Abstract: Structures and processes for improving radiation hardness and eliminating latch-up in integrated circuits are provided. An example process includes forming a first doped buried layer, a first well, and a second well, and using a first mask, forming a second doped buried layer only in a first region above the first doped buried layer and between at least the first well and the second well, where the first mask is configured to control spacing between the wells and the doped buried layers. The process further includes using a second mask, forming a vertical conductor located only in a second region above the first region and between at least the first well and the second well, where the vertical conductor is doped to provide a low resistance link between the second doped buried layer and at least a top surface of the substrate.Type: ApplicationFiled: October 28, 2020Publication date: February 11, 2021Inventors: David R. Gifford, Patrice M. Parris
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Patent number: 10825715Abstract: Structures and processes for improving radiation hardness and eliminating latch-up in integrated circuits are provided. An example process includes forming a first doped buried layer, a first well, and a second well, and using a first mask, forming a second doped buried layer only in a first region above the first doped buried layer and between at least the first well and the second well, where the first mask is configured to control spacing between the wells and the doped buried layers. The process further includes using a second mask, forming a vertical conductor located only in a second region above the first region and between at least the first well and the second well, where the vertical conductor is doped to provide a low resistance link between the second doped buried layer and at least a top surface of the substrate.Type: GrantFiled: November 8, 2018Date of Patent: November 3, 2020Assignee: Silicon Space Technologies CorporationInventors: David R. Gifford, Patrice M. Parris
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Publication number: 20200342070Abstract: Systems and methods related to learning-based analyzers (both supervised and unsupervised) for mitigating latch-up in integrated circuits are provided. An example method includes obtaining latch-up data concerning at least one integrated circuit configured to operate under a range of temperature conditions, where the at least one integrated circuit comprises a core portion including at least a plurality of devices each having one or more structural features formed using a lithographic process, and an input/output portion. The method further includes training the learning-based system based on training data derived from the latch-up data and a first layout rule concerning a first spacing between the core portion and the input/output portion. The method further includes using the learning-based system generating a second layout rule concerning the first spacing between the core portion and the input/output portion, where the second layout rule is different from the first layout rule.Type: ApplicationFiled: April 29, 2019Publication date: October 29, 2020Inventors: Patrice M. Parris, David R. Gifford, Bernd Lienhard
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Publication number: 20200152578Abstract: Structures and processes for improving radiation hardness and eliminating latch-up in integrated circuits are provided. An example process includes forming a first doped buried layer, a first well, and a second well, and using a first mask, forming a second doped buried layer only in a first region above the first doped buried layer and between at least the first well and the second well, where the first mask is configured to control spacing between the wells and the doped buried layers. The process further includes using a second mask, forming a vertical conductor located only in a second region above the first region and between at least the first well and the second well, where the vertical conductor is doped to provide a low resistance link between the second doped buried layer and at least a top surface of the substrate.Type: ApplicationFiled: November 8, 2018Publication date: May 14, 2020Inventors: David R. Gifford, Patrice M. Parris
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Publication number: 20160246675Abstract: An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.Type: ApplicationFiled: February 19, 2016Publication date: August 25, 2016Inventors: DAVID R. GIFFORD, KEVIN E. ATKINSON, JAMES A. JENSEN
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Patent number: 9268637Abstract: An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.Type: GrantFiled: March 15, 2014Date of Patent: February 23, 2016Assignee: SILICON SPACE TECHNOLOGY CORPORATIONInventors: David R. Gifford, Kevin E. Atkinson, James A. Jensen
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Patent number: 9201726Abstract: An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.Type: GrantFiled: March 2, 2015Date of Patent: December 1, 2015Assignee: SILICON SPACE TECHNOLOGY CORPORATIONInventors: Wesley H. Morris, David R. Gifford, Rex E. Lowther
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Publication number: 20150169400Abstract: An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.Type: ApplicationFiled: March 2, 2015Publication date: June 18, 2015Inventors: WESLEY H. MORRIS, DAVID R. GIFFORD, REX E. LOWTHER
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Patent number: 8972819Abstract: An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.Type: GrantFiled: November 21, 2012Date of Patent: March 3, 2015Assignee: Silicon Space Technology CorporationInventors: Wesley H. Morris, David R. Gifford, Rex E. Lowther
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Publication number: 20140281810Abstract: An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.Type: ApplicationFiled: March 15, 2014Publication date: September 18, 2014Inventors: DAVID R. GIFFORD, KEVIN E. ATKINSON, JAMES A. JENSEN
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Publication number: 20130166990Abstract: An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.Type: ApplicationFiled: November 21, 2012Publication date: June 27, 2013Inventors: Wesley H. Morris, David R. Gifford, Rex E. Lowther
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Patent number: 4929995Abstract: A bipolar transistor with a laterally elongated emitter and base so a laser can diffuse dopant from that emitter through that base to the corresponding collector.Type: GrantFiled: March 17, 1989Date of Patent: May 29, 1990Assignee: Honeywell Inc.Inventor: David R. Gifford
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Patent number: 4849365Abstract: A bipolar transistor with a laterally elongated emitter and base so a laser can diffuse dopant from that emitter through that base to the corresponding collector.Type: GrantFiled: February 16, 1988Date of Patent: July 18, 1989Assignee: Honeywell Inc.Inventor: David R. Gifford