Patents by Inventor David R. Gonzales

David R. Gonzales has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240084452
    Abstract: A tray for a vaporization vessel that includes a tray having a side wall, a bottom plate, one or more apertures that extend through the bottom plate, and a duct that extends through and from the bottom plate. The tray configured to support a solid reagent to be vaporized. A method of assembling the tray that includes forming a first tray that has the side wall and the bottom plate. A vaporization vessel that includes one or more of the trays.
    Type: Application
    Filed: October 13, 2023
    Publication date: March 14, 2024
    Inventors: Bryan C. HENDRIX, Scott L. Battle, David J. Eldridge, John N. Gregg, Jacob Thomas, Manuel F. Gonzales, Kenney R. Jordan, Benjamin H. Olson
  • Patent number: 6748558
    Abstract: A performance monitor system includes a core processor (115), a core processor associated device, such as a cache (123), and first logic, such as performance logic (127). The core processor (115) is operable to execute information. The core processor associated device provides a first signal (CACHE_PERF), which defines performance of the core processor associated device (123) during operation of the core processor (115). The first logic (127) is coupled to the core processor associated device (123) and monitors the first signal (CACHE_PERF) in response to a second signal (WPT0,1), which defines a match of user-settable attributes associated with the operation of the core processor (115).
    Type: Grant
    Filed: May 10, 2000
    Date of Patent: June 8, 2004
    Assignee: Motorola, Inc.
    Inventors: David R. Gonzales, Brian D. Branson, Jimmy Gumulja, William C. Moyer
  • Patent number: 5488688
    Abstract: A data processor (20) includes a diagnostic circuit (23) with a first-in, first-out memory (FIFO) (25) for storing sequential states of an internal bus, such as a program address bus. In one mode, the diagnostic circuit (23) halts a central processing unit (CPU) (21) and the FIFO (25) on the occurrence of an event condition, such as a hardware breakpoint. In a second mode, the diagnostic circuit (23) halts the FIFO (25) but keeps the CPU (21) in normal operation. Thus, the contents of the FIFO (25) may be examined through a serial port while the CPU (21) is executing instructions normally.
    Type: Grant
    Filed: March 30, 1994
    Date of Patent: January 30, 1996
    Assignee: Motorola, Inc.
    Inventors: David R. Gonzales, Gordon A. Carichner