Abstract: A performance monitor system includes a core processor (115), a core processor associated device, such as a cache (123), and first logic, such as performance logic (127). The core processor (115) is operable to execute information. The core processor associated device provides a first signal (CACHE_PERF), which defines performance of the core processor associated device (123) during operation of the core processor (115). The first logic (127) is coupled to the core processor associated device (123) and monitors the first signal (CACHE_PERF) in response to a second signal (WPT0,1), which defines a match of user-settable attributes associated with the operation of the core processor (115).

Abstract: A data processor (20) includes a diagnostic circuit (23) with a first-in, first-out memory (FIFO) (25) for storing sequential states of an internal bus, such as a program address bus. In one mode, the diagnostic circuit (23) halts a central processing unit (CPU) (21) and the FIFO (25) on the occurrence of an event condition, such as a hardware breakpoint. In a second mode, the diagnostic circuit (23) halts the FIFO (25) but keeps the CPU (21) in normal operation. Thus, the contents of the FIFO (25) may be examined through a serial port while the CPU (21) is executing instructions normally.