Abstract: An aiming guide system configured for connection to a bone plate including an aiming arm and a connection assembly. The aiming arm has a rigid body extending from a proximal end to a distal end with a plurality of aiming holes defined through the rigid body between the proximal end and the distal end thereof. The distal end defines an attachment slot through the body. The connection assembly is configured to engage an attachment screw hole of the bone plate and the attachment slot such that the aiming arm is fixed in position relative to the bone plate with each of the aiming holes aligned with a respective hole along the bone plate.

Abstract: The present invention provides methods and compositions for preparing 4-substituted 3-hydroxybutyric acid derivatives by halohydrin dehalogenase-catalyzed conversion of 4-halo-3-hydroxybutyric acid derivatives. The present invention further provides methods and compositions for preparing 4-halo-3-hydroxybutyric acid derivatives by ketoreductase-catalyzed conversion of 4-halo-3-ketobutyric acid derivatives The present invention also provides methods and compositions for preparing vicinal cyano, hydroxyl substituted carboxylic acid esters.

Abstract: The cooler support shelf is a rectangular platform having each of two corner sections of one side of the platform perpendicularly connected to separate vertical rails. The tops of the two rails are curved into hooks in the direction away from the platform. Diagonal support struts are connected from opposed sides of the platform to the lower part of each vertical rail. A horizontal support bar may extend between the connections of the diagonal support struts and the vertical rails. A hook and loop restraining strap is connected near the top of each vertical rail. The two straps can connect around the cooler to keep it in place on the platform.

Abstract: The present invention provides methods and compositions for preparing 4-substituted 3-hydroxybutyric acid derivatives by halohydrin dehalogenase-catalyzed conversion of 4-halo-3-hydroxybutyric acid derivatives. The present invention further provides methods and compositions for preparing 4-halo-3-hydroxybutyric acid derivatives by ketoreductase-catalyzed conversion of 4-halo-3-ketobutyric acid derivatives The present invention also provides methods and compositions for preparing vicinal cyano, hydroxyl substituted carboxylic acid esters.

Abstract: The present invention provides methods and compositions for preparing 4-substituted 3-hydroxybutyric acid derivatives by halohydrin dehalogenase-catalyzed conversion of 4-halo-3-hydroxybutyric acid derivatives. The present invention further provides methods and compositions for preparing 4-halo-3-hydroxybutyric acid derivatives by ketoreductase-catalyzed conversion of 4-halo-3-ketobutyric acid derivatives.

Abstract: The present invention provides methods and compositions for preparing 4-substituted 3-hydroxybutyric acid derivatives by halohydrin dehalogenase-catalyzed conversion of 4-halo-3-hydroxybutyric acid derivatives. The present invention further provides methods and compositions for preparing 4-halo-3-hydroxybutyric acid derivatives by ketoreductase-catalyzed conversion of 4-halo-3-ketobutyric acid derivatives The present invention also provides methods and compositions for preparing vicinal cyano, hydroxyl substituted carboxylic acid esters.

Abstract: The present invention provides methods and compositions for preparing 4-substituted 3-hydroxybutyric acid derivatives by halohydrin dehalogenase-catalyzed conversion of 4-halo-3-hydroxybutyric acid derivatives. The present invention further provides methods and compositions for preparing 4-halo-3-hydroxybutyric acid derivatives by ketoreductase-catalyzed conversion of 4-halo-3-ketobutyric acid derivatives.

Abstract: A computer architecture that includes a high speed, low pin bus that directly couples a microprocessor to the physical memory of the processor. Physical memory typically has a number of dynamic random access memory (DRAM) devices. The bus is a byte wide and has a data rate of approximately 500 Mbytes/sec. The high speed bus may be coupled with a conventional bus, so that conventional devices can communicate with the processor using existing bus protocols. The present invention includes a processor interface that allows the processor to communicate using the protocol of either bus. The interface also allows communication between devices on either bus. Also included is a system that incorporates cache memory on a high speed memory bus and a method for allowing I/O devices to be placed on both a conventional bus and the separate high speed bus.

Abstract: A computer architecture that includes a high speed, low pin bus that directly couples a microprocessor to the physical memory of the processor. Physical memory typically has a number of dynamic random access memory (DRAM) devices. The bus is a byte wide and has a data rate of approximately 500 Mbytes/sec. The high speed bus may be coupled with a conventional bus, so that conventional devices can communicate with the processor using existing bus protocols. The present invention includes a processor interface that allows the processor to communicate using the protocol of either bus. The interface also allows communication between devices on either bus. Also included is a system that incorporates cache memory on a high speed memory bus and a method for allowing I/O devices to be placed on both a conventional bus and the separate high speed bus.

Abstract: A computer architecture that includes a high speed, low pin bus that directly couples a microprocessor to the physical memory of the processor. Physical memory typically has a number of dynamic random access memory (DRAM) devices. The bus is a byte wide and has a data rate of approximately 500 Mbytes/sec. The high speed bus may be coupled with a conventional bus, so that conventional devices can communicate with the processor using existing bus protocols. The present invention includes a processor interface that allows the processor to communicate using the protocol of either bus. The interface also allows communication between devices on either bus. Also included is a system that incorporates cache memory on a high speed memory bus and a method for allowing I/O devices to be placed on both a conventional bus and the separate high speed bus.

Abstract: A computer architecture that includes a high speed, low pin bus that directly couples a microprocessor to the physical memory of the processor. Physical memory typically has a number of dynamic random access memory (DRAM) devices. The bus is a byte wide and has a data rate of approximately 500 Mbytes/sec. The high speed bus may be coupled with a conventional bus, so that conventional devices can communicate with the processor using existing bus protocols. The present invention includes a processor interface that allows the processor to communicate using the protocol of either bus. The interface also allows communication between devices on either bus. Also included is a system that incorporates cache memory on a high speed memory bus and a method for allowing I/O devices to be placed on both a conventional bus and the separate high speed bus.

Abstract: A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.

Abstract: A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process-compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.

Abstract: A process is described for producing M-CSF from bacteria. It includes: fermentation of bacteria containing M-CSF DNA; harvest of the fractions that contain the M-CSF protein (refractile bodies); primary recovery of the protein; solubilization and denaturation of refractile bodies; M-CSF refolding; purification by column chromatography and other methods; and formulation of the properly refolded M-CSF. This method is advantageous over prior methods in terms of yield and purity.

Abstract: A distributed method for arbitrating access to a common bus in a multiple processor environment is described. This method provides for fairness where multiple processors are vying for access to a global memory. An apparatus for arbitrating access to a common bus in a multiple processor environment is also described. This apparatus provides for priority determination of each processor upon system reset and provides for fairness where multiple processors are vying for access to a global memory.

Abstract: A method of transferring data in response to a read command in a computer system having a plurality of processors coupled to an address bus, a command bus and a data bus is described. A first processor generates and sends the read command to read a first data from a second processor. The second processor then determines with which one of (1) the first data and (2) a read response command and the first data it desires to respond to the read command. If the second processor determines to respond with the first data, then it acknowledges receipt of the read command and performs an ordered response in which the command and address buses are released and only the first data is later sent to the first processor via the data bus when available.

Abstract: A heat-shrinkable electrically shielding tubular article is provided with an electrically conductive lining on its inner surface, which lining is formed of a continuous coating of a metal which deforms without cracking during recovery so that after recovery the coating will remain continuous and adhered to the surface of the article. The coating may be formed of an alloy which softens without fully melting, at the recovery temperature of the article.