Abstract: A circuit for use in a phase lock loop including a first phase detector to detect a first phase error between input signals, the first phase detector obtaining the first phase error during a first time period, a second phase detector to detect a second phase error between the input signals, the second phase detector obtaining the second phase error during a second time period, the second time period being longer than the first time period, and a compensation circuit to compensate the first phase error with a portion of the second phase error signal.

Abstract: A data detectors have been invented featuring a fixed decision delays. The detector is comprised of a preliminary detector working on a single sample and releasing a few probably decisions and a signal, pace detector making a final selection among these probable decisions. The final decision is made based on a finite number of observation samples. The signal space detector consists of filter bank, slicers, and a Boolean logic (circuit?).

Abstract: A circuit for use in a phase locked loop includes pre-computation blocks for phase error detector and loop filter functions, a selection block (or multiplexer) of these pre-computed results based on detected (or reference signal) signal, and on ambiguity zone detector deriving the pre-computation blocks.

Abstract: A circuit for use in a phase lock loop including a first phase detector to detect a first phase error between input signals, the first phase detector obtaining the first phase error during a first time period, a second phase detector to detect a second phase error between the input signals, the second phase detector obtaining the second phase error during a second time period, the second time period being longer than the first time period, and a compensation circuit to compensate the first phase error with a portion of the second phase error signal.

Abstract: A method and apparatus for implementing a noise generator in an integrated circuit read channel to optimize the performance of the signal channel. In the preferred embodiment resistors are used to generate noise. The noise source is buffered and the noise signal passes through a pre-amplifier stage. A differential current digital-to-analog converter controlled multiplier cell controls the amplitude of the noise signal. A switch connects the noise signal to a differential current output buffer, which is coupled to a signal channel.