Patents by Inventor David R. Helms

David R. Helms has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240076123
    Abstract: A sanitary product disposal container includes a container housing having a movable housing top cover. A cover hinge assembly allows the top cover to pivot between open and closed positions. Accordingly, a used feminine hygiene product may be placed in the interior space of the container housing in the open position of the housing top cover while minimizing touching the container housing to open the housing top cover. The housing may be selectively opened to facilitate removal of the used feminine hygiene products from the interior space all without exposure to the used products or the escape of unpleasant odors.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 7, 2024
    Inventors: Richard R. Bing, Megan Kathryn Helms, David Steven Mesko, Emily Yeager, Pil Ho Chung, Joshua Meador, Marco Perry, Brooke Williams
  • Patent number: 9819316
    Abstract: A wide bandgap voltage reference circuit generates a temperature stable negative bias reference voltage for use in wide bandgap circuits. The reference circuit uses field effect transistor (FET) based source feedback. It can also be used as source feedback in high power high bandgap device applications, where constant current is required over process and thermal variations.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: November 14, 2017
    Assignee: Lockheed Martin Corporation
    Inventor: David R. Helms
  • Publication number: 20160308498
    Abstract: A wide bandgap voltage reference circuit generates a temperature stable negative bias reference voltage for use in wide bandgap circuits. The reference circuit uses field effect transistor (FET) based source feedback. It can also be used as source feedback in high power high bandgap device applications, where constant current is required over process and thermal variations.
    Type: Application
    Filed: April 20, 2016
    Publication date: October 20, 2016
    Inventor: David R. Helms
  • Patent number: 9240756
    Abstract: A two-stage RF amplifier comprising first and second transistors arranged in cascode. The first transistor cooperatively connected to an input RF signal source through a parallel RC network. The gate of the second transistor terminated with a lossy connection.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: January 19, 2016
    Assignee: Lockheed Martin Corporation
    Inventors: David R. Helms, James Sweder, Brett Ingersoll
  • Patent number: 9219450
    Abstract: A two-stage RF amplifier comprising first and second transistors arranged in cascode. An input stage includes a common source transistor having a gate terminal responsive to an input signal and an output stage includes a common gate transistor having a source terminal operatively connected to the drain terminal of the common source transistor. A shunt feedback network is arranged between a drain terminal of the common gate transistor and the gate terminal of the common source transistor. A source feedback network is arranged between the source terminal of the common source transistor and a reference potential. A common gate feedback network is arranged between the drain terminal of the common gate transistor and a gate terminal of the common gate transistor. And a termination feedback network is arranged in series between the reference potential and the gate terminal of the common gate transistor.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: December 22, 2015
    Assignee: Lockheed Martin Corporation
    Inventors: David R. Helms, Peter W. Fox, Jr., Thomas P. Higgins, William G. Trueheart, Jr.
  • Patent number: 8963645
    Abstract: An integrated circuit amplifier comprises: a first planar substrate having an upper surface and a lower surface; a second planar substrate having an upper surface and a lower surface, the lower surface of the second planar substrate physically affixed to the upper surface of the first planar substrate; at least one transistor pair comprising a first and second transistor, formed in the upper surface of the second planar substrate; and a conductor electrically coupling a drain electrode of the first transistor to a source electrode of the second transistor. The first substrate material may have a higher thermal conductivity than the second substrate material. The first material may be Silicon Carbide and may have a thickness of about 10 mils. The second material may be Gallium Arsenide and may have a thickness of about 1 to 2 mils.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: February 24, 2015
    Assignee: Lockheed Martin Corporation
    Inventors: David R. Helms, John Ditri, Stuart R. Ducker, Dana J. Sturzebecher
  • Patent number: 8918068
    Abstract: A radio frequency (RF) power limiter including a signal conductor having an input end and an output end and first and second limiter stages. The first limiter stage comprises a plurality of stacked diode strings arranged in anti-parallel with respect to the signal conductor. The second limiter stage comprises a second plurality of stacked diode strings arranged in anti-parallel with respect to the signal conductor. An all pass filter is arranged between the first and second limiter stages.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: December 23, 2014
    Assignee: Lockheed Martin Corporation
    Inventors: David R. Helms, Dana J. Sturzebecher
  • Patent number: 8466747
    Abstract: An integrated circuit comprises a GaAs substrate thermally and mechanically mounted on a SiC substrate. The GaAs substrate is doped to define first and second transistors. Circuit conductors are defined on the GaAs substrate, which conductors interconnect the source of the first transistor to neutral and the drain to the source of the second transistor. Conductors connect the gate of the second transistor to neutral, to define a cascode amplifier. The SiC substrate supports first and second matching circuits, one of which is connected to the gate of the first transistor, and the other of which is connected to the drain of the second transistor.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: June 18, 2013
    Assignee: Lockheed Martin Corporation
    Inventors: David R. Helms, John Ditri, Stuart R. Ducker, Dana J. Sturzebecher
  • Patent number: 6448858
    Abstract: A side fed RF amplifier comprising a plurality of transistors connected in parallel such that the base, emitter, and collector leads of each transistor are electrically connected to the base, emitter, and collector leads, respectively, of all other transistors. A common, physical point interconnects the power amplifier current source and the base leads of every transistor. The transistors are arranged such that the impedance between the common physical point and the base lead of any one transistor is substantially equivalent to the impedance between the common point and the base lead of any other transistor within the power amplifier.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: September 10, 2002
    Assignee: International Business Machines Corporation
    Inventors: David R. Helms, Philip Antognetti
  • Patent number: 5491450
    Abstract: A low power consumption amplifier that is essentially insensitive to the process used to fabricate the active devices of the amplifier employs feedback to minimize variations in electrical characteristics of the devices. For weight-sensitive microwave applications, a high electron mobility transistor (HEMT) or a pseudomorphic high electron mobility transistor (PHEMT) may be selected as an active device for each stage of the amplifier. HEMTs and PHEMTs typically exhibit greater device gain than do MESFETs, especially at the upper portion of X-band and above, so that a HEMT- or PHEMT-based stage of an amplifier where additional overall gain is required, can be achieved without significantly adversely affecting power consumption demands, and attendant electrical energy storage/generation requirements while achieving and/or maintaining an overall flat gain characteristic of the amplifier.
    Type: Grant
    Filed: June 1, 1993
    Date of Patent: February 13, 1996
    Assignee: Martin Marietta Corporation
    Inventors: David R. Helms, Michael J. Fithian
  • Patent number: 5049841
    Abstract: An electronically reconfigurable digital pad attenuator is disclosed using selectively controlled segmented field effect transistors in a passive, non-gain state as the principal impedance elements. The attenuator may be fabricated in the monolithic microwave integrated circuit (MMIC) format with a segmented gate field effect transistor being connected in each of the separate branches of a Pi pad, Tee pad, or Bridged Tee pad attenuator configuration. The individual FET segments are maintained in a high admittance "ON" state or a low admittance "OFF" state in accordance with the binary control potentials applied to the gate of each segment, the principal electrodes being maintained at a zero potential difference. The attenuation then becomes a function of the binary gate potentials applied to each segment and assumes one of a set of well-defined discrete values. The attenuator consumes minimum power, provides attenuation steps that are independent of GaAs MMIC fabrication process tolerances, i.e.
    Type: Grant
    Filed: July 11, 1990
    Date of Patent: September 17, 1991
    Assignee: General Electric Company
    Inventors: Paul D. Cooper, Paul A. Bourdelais, Anthony W. Jacomb-Hood, John A. Windyka, David R. Helms, Ronald J. Naster
  • Patent number: 4947136
    Abstract: The invention relates to a variable gain distributed amplifier for use at microwave frequencies, and fabricated in a monolithic microwave integrated circuit format. In the amplifier, the attenuation is varied, based upon digital control of a dual gate segmented FET. The amplifier has a nearly flat insertion phase and amplitude response, and an insertion phase response that varies only slightly between gain settings. The amplifier employs segmented dual gate field effect transistors as the gain elements, having their signal input and signal output electrodes which provide shunt capacities (C.sub.G1S, C.sub.DS) interconnected with serial inductances to form separate low pass transmission lines having relatively high cut-off frequencies. The amplifier has means to insure stability and uses Chebyshef equal ripple techniques to linearize the amplitude and insertion phase response.
    Type: Grant
    Filed: September 18, 1989
    Date of Patent: August 7, 1990
    Assignee: General Electric Company
    Inventor: David R. Helms