Patents by Inventor David R. Lindley

David R. Lindley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Address counter test mode for memory device
    Patent number: 6813741
    Abstract: A memory having a circuit including a built-in address counter with a test mode. The address counter may be used to generate the memory array addressing for the different array test patterns. The circuit may comprise a logic circuit and a counter circuit. The logic circuit may be configured to generate one or more control signals in response to one or more control inputs. The counter circuit may be configured to generate a first counter output and a second counter output in response to (i) the control outputs and (ii) one or more inputs. The counter may comprise a first portion configured to generate the first counter output and a second portion configured to generate the second counter output.
    Type: Grant
    Filed: May 18, 2000
    Date of Patent: November 2, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: George M. Ansel, David R. Lindley, Jeffrey W. Gossett, Junfei Fan, Andrew L. Hawkins, Michael D. Carlson
  • Electrical ID method for output driver
    Patent number: 6353336
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first output signal in response to one or more first input signals. The second circuit may be configured to generate a second output signal in response to one or more second input signals. The first and second output signals may be presented to a bond pad.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: March 5, 2002
    Assignee: Cypress Semiconductor Corp.
    Inventors: David R. Lindley, William G. Baker, Jeffery Scott Hunt
  • Address counter test mode for memory device
    Patent number: 6078637
    Abstract: A memory having a circuit including a built-in address counter with a test mode. The address counter may be used to generate the memory array addressing for the different array test patterns. The circuit may comprise a logic circuit and a counter circuit. The logic circuit may be configured to generate one or more control signals in response to one or more control inputs. The counter circuit may be configured to generate a first counter output and a second counter output in response to (i) the control outputs and (ii) one or more inputs. The counter may comprise a first portion configured to generate the first counter output and a second portion configured to generate the second counter output.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: June 20, 2000
    Assignee: Cypress Semiconductor Corp.
    Inventors: George M. Ansel, David R. Lindley, Jeffrey W. Gossett, Junfei Fan, Andrew L. Hawkins, Michael D. Carlson