Abstract: A computer system is disclosed that includes: a communications bus implemented in accordance with an Inter-IC bus specification; a bus controller coupled to the communications bus; a send machine coupled between a host processor and the bus controller; and a first-in first-out (FIFO) buffer coupled to the send machine and coupled between the host processor and the bus controller.

Abstract: A machine-readable identification register is provided on each cell of a cellular computer system. The identification register is read during system startup to identify a processor type, which may include an instruction set architecture (ISA), associated with the cell. The processor type information is used to ensure that a compatible boot image is provided to processors of the cell. In another embodiment, the system management subsystem has a version selection flag. When the version selection flag is in a first state, the compatible boot image provided to processors of the cell is a current boot image; with the selection flag in a second state the compatible boot image provided to processors of the cell is an older edition of the boot image.

Abstract: Techniques and apparatus are disclosed for detecting and responding to the malfunction of a host coupled to a communications bus through a bus transceiver.

Abstract: A system-event core for monitoring system events in a cellular computer system within a parent computer system is provided. The system-event core comprises: a control register block for each cell computer system configured to mask one or more system events and configurable to be masked by a system-event manager, an input/output block operable to communicate with a computer bus, a register block operable to store data about system events, and interrupt generation logic operable to control interrupts for the cellular computer system.

Abstract: Disclosed are systems and methods for providing access to bus-mastered system resources comprising disposing a bus multiplexer between a first bus and a bus access arbiter, wherein the first bus is coupled to at least one system resource for which bus access is arbitrated by the bus access arbiter, and controlling the bus multiplexer to couple a second bus to the first bus thereby providing a link between the first bus and the second bus bypassing the bus access arbiter.

Abstract: The invention provides a method of implementing firmware updates to programmable parts within circuit boards on a manufacturing line. An image file of firmware for each of the parts is created and stored on a firmware server. The programmable parts are preferably integrated with the printed circuit boards; each of the boards networks to the firmware server by connection with an interface server, such that the image files download to the circuit board for programming the board's internal programmable parts. Networking between the parts and the firmware server can include communications across the Internet and/or one or more area networks. Multiple interface servers may be integral with the products incorporating the programmable parts so that many products may be updated concurrently.

Abstract: Logic apparatus filters noise signals on a signal line to a digital circuit. An edge detector determines one or more edges of the noise signals relative to a fast clock. Signals indicative of the edges asynchronously reset a timer; the timer clocks the latch of the signal line when the signal line is stable, and without noise signals detected by the edge detector, for a period defined by a slow clock. The slow clock is slower than the fast clock by several orders of magnitude. The edge detector may be constructed by one flip-flop and an XOR gate. A second flip flop couples to the signal line and the output of the timer to pass through the latched value of the signal line to the digital circuit when clocked by the timer.

Abstract: A method of updating programmable device configuration code stored in EEPROMs of a system is operable on complex systems having separate management and system processors. The method includes executing a sequence for updating programmable device configuration code on a management processor of the system including erasing the EEPROMs, writing at least one block of configuration code to the EEPROMs, and checking for errors after writing. The errors checked for include failure of a FIFO to empty. Upon detecting errors, the method includes automatically retrying writes. Embodiments of the method are operable on systems having multiple serial busses interconnecting EEPROMs to a common configuration logic, and on systems having multiple management processors each capable of accessing the common configuration logic.

Abstract: Techniques and apparatus are disclosed for detecting and responding to the malfunction of a host coupled to a communications bus through a bus transceiver.

Abstract: A bus bridge is capable of transferring information between a first serial bus and a target serial bus. The bridge is capable of operating as a bus slave on the first serial bus, and as a bus master on the target serial bus. The first serial bus in a particular embodiment is an IIC serial bus, while the target serial bus is a JTAG bus. There may be additional target serial busses, and there is a selection apparatus whereby commands may be directed to a particular target serial bus.

Abstract: Disclosed are systems and methods for providing access to bus-mastered system resources comprising disposing a bus multiplexer between a first bus and a bus access arbiter, wherein the first bus is coupled to at least one system resource for which bus access is arbitrated by the bus access arbiter, and controlling the bus multiplexer to couple a second bus to the first bus thereby providing a link between the first bus and the second bus bypassing the bus access arbiter.

Abstract: A DC—DC voltage converter has a controller, two switches, a transformer and two rectifying diodes. The transformer has a first winding, a second winding and a center tap. Input voltage is connected between the center tap and ground. An anode of each diode is connected to the outer ends of the two windings and the cathodes of the two diodes are connected together to provide a positive output with respect to ground. Each switch is connected between an outer end of one winding and ground. The controller generates control signals to turn the switches on and off for limited periods of time in phase opposition to alternately connect the outer ends of the first and second winding to ground to cause current to flow alternatively in one of the windings and induce a voltage in the other winding that is additive to the input voltage, thereby providing an output voltage greater than the input voltage.

Abstract: A system-event core for monitoring system events in a cellular computer system within a parent computer system is provided. The system-event core comprises: a control register block for each cell computer system configured to mask one or more system events and configurable to be masked by a system-event manager, an input/output block operable to communicate with a computer bus, a register block operable to store data about system events, and interrupt generation logic operable to control interrupts for the cellular computer system.

Abstract: A system for providing basic system control functions upon failure of all management processors in a computer system. During normal system operation, a plurality of management processors monitor system sensors that detect system power, temperature, and cooling fan status, and make necessary adjustments. Each management processor normally provides an output signal indicating that it is operating property. A high-availability controller monitors each of these signals to verify that there is at least one operating management processor. When none of the processors indicate that they are operating properly, the high-availability controller monitors the system sensors and updates system indicators. If a problem develops, such as failure of a power supply or a potentially dangerous increase in temperature, the high-availability controller sequentially powers down the appropriate equipment to protect the system from damage.

Abstract: The invention provides methods and logic for determining the source of a processor reset in a system having a processor and a plurality of processor reset sources. The plurality of processor reset sources couple to a corresponding plurality of RS latches. One of the RS latches sets in response to a processor reset generated by one of the processor resets. That one RS latch writes logic high to a dedicated register of a read register. After rebooting, the processor reads the read register to determine which register is logic high, corresponding to the source that generated the reset. The read register is reset by writing logic high into a write register, thereby resetting the set RS latch and clearing the logic high register of the read register. The processor writes logic low to all write register bits to clear enable the RS latches so that subsequent processor resets are identified.

Abstract: Logic apparatus filters noise signals on a signal line to a digital circuit. An edge detector determines one or more edges of the noise signals relative to a fast clock. Signals indicative of the edges asynchronously reset a timer; the timer clocks the latch of the signal line when the signal line is stable, and without noise signals detected by the edge detector, for a period defined by a slow clock. The slow clock is slower than the fast clock by several orders of magnitude. The edge detector may be constructed by one flip-flop and an XOR gate. A second flip flop couples to the signal line and the output of the timer to pass through the latched value of the signal line to the digital circuit when clocked by the timer.

Abstract: A DC-DC voltage converter comprises a controller, two switches, a transformer and two rectifying diodes. The transformer has a first winding, a second winding and a center tap. Input voltage in connected between the center tap and ground. An anode of each diode is connected to the outer ends of the two windings and the cathodes of the two diodes are connected together to provide a positive output with respect to ground. Each switch is connected between an outer end of one windings and ground. The controller generates control signals to turn the switches on and off for limited periods of time in phase opposition to alternately connect the outer ends of the first and second winding to ground to cause current to flow alternatively in one of the windings and induce a voltage in the other winding that is additive to the input voltage, thereby providing an output voltage greater than the input voltage.

Abstract: A method of updating programmable device configuration code stored in EEPROMs of a system is operable on complex systems having separate management and system processors. The method includes executing a sequence for updating programmable device configuration code on a management processor of the system including erasing the EEPROMs, writing at least one block of configuration code to the EEPROMs, and checking for errors after writing. The errors checked for include failure of a FIFO to empty. Upon detecting errors, the method includes automatically retrying writes. Embodiments of the method are operable on systems having multiple serial busses interconnecting EEPROMs to a common configuration logic, and on systems having multiple management processors each capable of accessing the common configuration logic.

Abstract: A method of debugging a system by analyzing transactions of a serial intra-system bus is particularly applicable to IIC or SPI intra-system busses. The method includes steps of capturing frames of the bus in a capture data file, extracting frames from the capture data file; checking frames for out-of-bounds addresses; and decoding an address of frames to identify a particular slave device type. Once a particular device type is identified, state changes indicated in frames are tracked with a computer model of the slave device; and state error information is recorded when frames indicate state changes that are not permissible state changes of the slave device.

Abstract: The invention provides a method of implementing firmware updates to programmable parts within circuit boards on a manufacturing line. An image file of firmware for each of the parts is created and stored on a firmware server. The programmable parts are preferably integrated with the printed circuit boards; each of the boards networks to the firmware server by connection with an interface server, such that the image files download to the circuit board for programming the board's internal programmable parts. Networking between the parts and the firmware server can include communications across the Internet and/or one or more area networks. Multiple interface servers may be integral with the products incorporating the programmable parts so that many products may be updated concurrently.