Abstract: In-circuit-emulation of an integrated circuit permits location and identification of optional emulation resources. Each emulation resource is assigned a memory address. The in-circuit-emulation generates a special memory access to memory addresses. If the special memory access corresponds to the address of an emulation resource, the emulation resource responds with an acknowledgement and a corresponding identification number. Nonemulation circuits do not respond to the special memory access. This technique permits manufacture of plural integrated circuits with corresponding sets of emulation resources, where an emulation program can determine the available resources for the particular integrated circuit. The emulation resources preferrably includes a set of emulation resources common to all integrated circuits with predetermined memory addresses and a predetermined identification numbers as well as optional emulation resources.

Abstract: A reconfigurable datapath (13b), which may be alternatively configured for various debug modes. These modes include a breakpoint mode (20), counter mode (30a-30c), DMA mode (40), and PSA mode (50). Each configuration uses one or more of two bitcell units: a register bitcell unit (60) and a comparator bitcell unit (70). The inputs and interconnections of these bitcell units (60, 70) determine the configuration, and hence the mode, for which they are to be used.

Abstract: Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated processor stops processing instructions in response to a debug event. A real-time mode of operation is provided in which the processor stops processing background instructions in response to a debug event, but in which high priority interrupts are still processed. While running or suspended, the emulation circuitry can jam an instruction into the instruction register of the processor to cause processor resources to be read or written on behalf of the emulation circuitry. An embodiment of a processor core is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks.

Abstract: In-circuit-emulation of an integrated circuit including a digital data processor capable of executing program instructions selectively assigns emulation resources to either the emulation function or the application program. Each emulation resource can have three states: unassigned; an emulation state assigned to emulation function; or an application state assigned to the application program. An emulation resource in the unassigned state may be assigned to emulation or application by writing to a predetermined data register. Emulation resources assigned to emulation return to unassigned state upon a test logic reset. Emulation resources assigned to the application return to the unassigned state upon an integrated circuit logic reset.

Abstract: Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated processor stops processing instructions in response to a debug event. A real-time mode of operation is provided in which the processor stops processing background instructions in response to a debug event, but in which high priority interrupts are still processed. Interrupts are classified and processed accordingly when the processor is stopped by a debug event. While suspended for a debug event, a frame counter keeps track of interrupt debug state if multiple interrupts occur. While running or suspended, the emulation circuitry can jam an instruction into the instruction register of the processor to cause processor resources to be read or written on behalf of the emulation circuitry. Read/write transactions are qualified by an expected frame count to maintain correspondence between test host software and multiple debug/interrupt events.

Abstract: Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated processor stops processing instructions in response to a debug event. A real-time mode of operation is provided in which the processor stops processing background instructions in response to a debug event, but in which high priority interrupts are still processed. Interrupts are classified and processed accordingly when the processor is stopped by a debug event. While suspended for a debug event, a frame counter keeps track of interrupt debug state if multiple interrupts occur. While running or suspended, the emulation circuitry can jam an instruction into the instruction register of the processor to cause processor resources to be read or written on behalf of the emulation circuitry. Read/write transactions are qualified by an expected frame count to maintain correspondence between test host software and multiple debug/interrupt events.

Abstract: Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated processor stops processing instructions in response to a debug event. A real-time mode of operation is provided in which the processor stops processing background instructions in response to a debug event, but in which high priority interrupts are still processed. Interrupts are classified and processed accordingly when the processor is stopped by a debug event. While suspended for a debug event, a frame counter keeps track of interrupt debug state if multiple interrupts occur. While running or suspended, the emulation circuitry can jam an instruction into the instruction register of the processor to cause processor resources to be read or written on behalf of the emulation circuitry. Read/write transactions are qualified by an expected frame count to maintain correspondence between test host software and multiple debug/interrupt events.

Abstract: Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated processor stops processing instructions in response to a debug event. A real-time mode of operation is provided in which the processor stops processing background instructions in response to a debug event, but in which high priority interrupts are still processed. Interrupts are classified and processed accordingly when the processor is stopped by a debug event. While suspended for a debug event, a frame counter keeps track of interrupt debug state if multiple interrupts occur. While running or suspended, the emulation circuitry can jam an instruction into the instruction register of the processor to cause processor resources to be read or written on behalf of the emulation circuitry. Read/write transactions are qualified by an expected frame count to maintain correspondence between test host software and multiple debug/interrupt events.

Abstract: A processor core is provided that is a programmable digital signal processor (DSP). The microprocessor is operable to execute a sequence of instructions obtained from an instruction bus and has program counter circuitry for providing a first instruction address to the instruction bus. An instruction buffer is operable to hold at least a first instruction of the sequence of instructions obtained from the instruction bus. Breakpoint event generation circuitry is connected to the instruction bus and is operable to detect a designated mark instruction and a designated chain instruction in the sequence of instructions. Tag circuitry is associated with the instruction buffer and is operable to hold a mark tag and a chain tag, and is further operable to be set in response to the breakpoint event circuitry. An instruction execution pipeline is connected to receive the sequence of instructions from the instruction buffer register along with respective mark tags and chain tags from the tag circuitry.

Abstract: A processor (16) is disclosed that has real-time execution control for debug functions. The processor (16) includes processor circuitry operable to execute embedded code (19) where the embedded code includes background code and foreground code. The processor (16) also includes debug circuitry interfacing with the processor circuitry and operable to communicate with a debug host (12). The debug circuitry is operable to receive a debug halt command from the debug host (12). After receipt of the debug halt command, the processor circuitry is operable to suspend execution of the embedded code (19) to allow debug of the embedded code (19). The processor circuitry is further operable, while execution of the embedded code (19) is suspended, to respond to an enabled interrupt by executing foreground code associated with the enabled interrupt.

Abstract: An integrated circuit (12) includes a processor (17) having an instruction execution pipeline (22). The pipeline has a plurality of successive stages (26-42) which correspond to respective successive phases of instruction execution. Instructions being executed move successively through the stages (26-42). A flattener section (18) is provided in the integrated circuit (12), and holds the state of certain pipeline signals until subsequent points in time. This permits various signals generated at different points in time during execution of an instruction to all be simultaneously available at a later point in time. A selector section (19) of the integrated circuit (12) selects either the output of the flattener section (18) or certain pipeline signals to be exported off the integrated circuit.