Abstract: In a printed wiring board, a plurality of stacked innerlayer panels have capacitors connected in parallel by connecting a first electrode of a first panel with a first electrode of a second panel, and similarly connecting second electrodes of the first and second panels. The innerlayer panel having capacitors connected in parallel provides a high capacitance in a small x-y area. An alternate printed wiring board has a capacitor having a first foil electrode, and second and third electrodes located on opposite sides of the first foil electrode. Yet another printed wiring board has capacitors formed as an array of discrete foil electrodes spaced from an array of discrete printed electrodes. Forming discrete interconnected electrodes allows the electrodes to be fired without excessive thermal coefficient of expansion stresses damaging the electrodes.

Abstract: A printed wiring board (PWB) has stacked innerlayer panels comprised of passive circuit elements. The passive elements can include capacitors with electrode terminations located within the footprints of the capacitor electrodes. The capacitor terminations are therefore closely spaced, reducing the capacitors' contributions to loop inductance in the innerlayer. Capacitor terminations within the electrode footprints also reduce the PWB board surface area used in forming the capacitors.