Abstract: A foundation for a system for protecting a surface is disclosed. The foundation comprises a base, a suction assembly, a shield and one or more supports. The suction assembly may include a suction member having a rim, and a pump. The suction member is configured to be releasably sealed against the surface. The shield may be mounted to the outer face of the base. The shield is disposed opposite to the suction member and is configured to obstruct penetration by a fastener into the portion of the outer face covered by the shield. The one or more supports are mounted to the outer face. Each support includes a ledge that extends outward from the base. Also disclosed is a system for boarding-up a window disposed in a structure.

Abstract: A foundation for a system for protecting a surface is disclosed. The foundation comprises a base, a suction assembly, a shield and one or more supports. The suction assembly may include a suction member having a rim, and a pump. The suction member is configured to be releasably sealed against the surface. The shield may be mounted to the outer face of the base. The shield is disposed opposite to the suction member and is configured to obstruct penetration by a fastener into the portion of the outer face covered by the shield. The one or more supports are mounted to the outer face. Each support includes a ledge that extends outward from the base. Also disclosed is a system for boarding-up a window disposed in a structure.

Abstract: A storage system caches logical-to-physical address table entries read in volatile memory. The logical-to-physical address table entries are stored in codewords. The storage system can vary a number or size of an entry in a codeword. Additionally or alternatively, each codeword can store both complete and partial logical-to-physical address table entries. In one example, a codeword having 62 bytes of data and two bytes of error correction code stores 15 complete logical-to-physical address table entries and one partial logical-to-physical address table entry, where the remainder of the partial entry is stored in another codeword. This configuration strikes a good balance between storage space efficiency and random-access write performance.

Abstract: Embodiments of the invention are directed to a system, method, or computer program product for providing a pre-arrears learning system with multi-channel cognitive resource application integration on front and back end applications. The system comprises a hub or workstation for representatives while also allowing for multi-channel cognitive resource application integration as a communication liaison with the user product identification. The system may identify key words during the interaction and provide those points to an representative via a storyboard. Furthermore, the system provides a strategy decision engine for product matching for the user, which allows the representative to mirror graphical user interfaces with the user device for product application.

Abstract: An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data. Various techniques may be employed for controlling the latency and sequencing of these operations, and the subsystems within the canceller may use different processing clock speeds.

Abstract: An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data. Various techniques may be employed for controlling the latency and sequencing of these operations, and the subsystems within the canceller may use different processing clock speeds.

Abstract: An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data. Various techniques may be employed for controlling the latency and sequencing of these operations, and the subsystems within the canceller may use different processing clock speeds.

Abstract: An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data. Various techniques may be employed for controlling the latency and sequencing of these operations, and the subsystems within the canceller may use different processing clock speeds.

Abstract: An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data. Various techniques may be employed for controlling the latency and sequencing of these operations, and the subsystems within the canceller may use different processing clock speeds.

Abstract: A system for registering print media includes a media tray configured to hold a plurality of sheets of print media, a pick assembly configured to pick a sheet of the print media from the media tray and route the sheet to a media path, and a registration assembly positioned in the media path after the pick assembly. The registration assembly is configured to sense the sheet in the media path and operate for a predetermined time based on an amount of the print media in the media tray to register the sheet in the media path such that the predetermined time increases as the amount of the print media in the media tray decreases.

Abstract: A system for registering print media includes a media tray configured to hold a plurality of sheets of print media, a pick assembly configured to pick a sheet of the print media from the media tray and route the sheet to a media path, and a registration assembly positioned in the media path after the pick assembly. The registration assembly is configured to sense the sheet in the media path and operate for a predetermined time based on an amount of the print media in the media tray to register the sheet in the media path such that the predetermined time increases as the amount of the print media in the media tray decreases.

Abstract: A timing-reference circuit is employed by a multi-time-based system in which a timing reference is required for system processing. The timing-reference circuit may be used in a wireless receiver in which one or more transmitted signals are received as multipath signals, each corresponding to a different time reference. The timing-reference circuit is configured for selecting at least one received signal in a set of multipath signals as a timing reference, tracking the timing reference with a virtual timing reference, and synchronizing receiver processing to the virtual timing reference, even when the actual timing reference from which the virtual reference was derived vanishes. The timing-reference circuit provides for re-acquisition of a new timing reference when the virtual reference no longer qualifies as a timing reference.

Abstract: Ring access control circuitry comprises a receive interface, a host interface coupled to the receive interface, a mate interface coupled to the host interface, a flow control agent coupled to the mate interface, a transmit interface coupled to the flow control agent, and a wrap path coupled from between the flow control agent and the transmit interface to between the receive interface and the host interface. A wrap is initiated over the wrap path in response to a link failure. The ring being controlled could be a resilient packet ring.

Abstract: Ring access control circuitry comprises a receive interface, a host interface coupled to the receive interface, a mate interface coupled to the host interface, a flow control agent coupled to the mate interface, a transmit interface coupled to the flow control agent, and a wrap path coupled from between the flow control agent and the transmit interface to between the receive interface and the host interface. A wrap is initiated over the wrap path in response to a link failure. The ring being controlled could be a resilient packet ring.

Abstract: A status queue in a host and a control queue in a segmentation and reassembly (SAR) subsystem are on opposite sides of a host bus in a control plane. Buffer descriptors in the host and the SAR and buffers in the host are in a data plane. To transfer cell payloads to a first line interfacing the SAR, the host writes the SAR that it has such cell payloads. The host writes the host buffer descriptors into the control queue to obtain the transfer of the buffer payload to the first line. The SAR writes the status queue when the transfer has been completed. To transfer cell payloads to the host memory, the host writes into the control queue the address of the buffers to receive the payload from the SAR. The SAR then writes the buffer descriptors to the status queue to obtain the transfer of the cell payloads to the buffers. Each of the control and status queues may be respectively considered to constitute two (2) control queues and two (2) status queues.

Abstract: Data (e.g. legacy LAN traffic) segmented into packets provide a header and a cell payload for each cell in each packet. The cell payloads are transferred to a region address in a host memory in accordance with determinations by a control memory. When the cell payload is to be transmitted from the host memory, the cell payload for a particular region address is combined with the header stored in the control memory for such address. Streaming data (e.g. voice or video) occurs at a regular rate and is not necessarily broken into packets. The streaming data is segmented to provide cell headers and cell payloads. The cell payloads are then transferred to a host receive FIFO in accordance with a determination by the control memory and are stored in a data sink. Cell payloads from a data source are transferred into a host transmit FIFO at a particular rate and are transferred from the host transmit FIFO preferably at a substantially constant rate higher than the particular rate.

Abstract: A borderless inkjet printer includes a hollow open end platen having a block of ink absorbent material disposed there within and exposed to a plurality of inkjet cartridges. A front set and a rear set of upstanding cockle ribs extend upwardly from the platen a sufficient distance to substantially prevent either a leading edge and a trailing edge of a sheet of print medium travel across a print zone within the printer from making contact with the absorbent material. A print engine having at least one print head travels in a rectilinear path above the print zone to eject ink droplets onto edge portions of the print medium to provide a borderless print image thereon.

Abstract: An edge device for an ATM system includes a fire wall protection which proactively limits the number of cells per connection provided to the devices connected to the edge device. The edge device may be connected to ethernets, LANs, frame relay networks, communication equipment, work stations, or various other computer and communication equipment. The edge device preferably includes a counter for each connection associated with the ATM system. The counter is decremented each time a memory location in the host memory is utilized and incremented whenever the memory location is relieved of storing the data cell. An SAR unit operates to proactively prevent congestion by limiting each connection to a particular number of storage elements.

Abstract: A status queue in a host and a control queue in a segmentation and reassembly (SAR) subsystem are on opposite sides of a host bus in a control plane. Buffer descriptors in the host and the SAR and buffers in the host are in a data plane. To transfer cell payloads to a first line interfacing the SAR, the host writes the SAR that it has such cell payloads. The host writes the host buffer descriptors into the control queue to obtain the transfer of the buffer payload to the first line. The SAR writes the status queue when the transfer has been completed. To transfer cell payloads to the host memory, the host writes into the control queue the address of the buffers to receive the payload from the SAR. The SAR then writes the buffer descriptors to the status queue to obtain the transfer of the cell payloads to the buffers. Each of the control and status queues may be respectively considered to constitute two (2) control queues and two (2) status queues.

Abstract: A header and a payload in a cell are separated for transfer between a cell interface and a host memory. The header is transferred to a control memory. For transfer to the host memory, the control memory initially provides a host-memory region address and the region length. The payload is recorded in such region. The control memory also provides a second host-memory region address, and length, when the payload length exceeds the payload length in the first address region. For transfer from the host memory to the cell interface, the control memory provides a host memory region address and the header combines the header and the payload and passes the combination to the cell interface. Cells from different sources (i.e. terminals) are scheduled at table positions dependent upon their individual transfer rates. The cells at the scheduled positions are normally transferred in time slots corresponding to such positions.