Patents by Inventor David R. Mucha

David R. Mucha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Neural network instruction streaming
    Patent number: 11475311
    Abstract: An artificial neural network is implemented via an instruction stream. A header of the instruction stream and a format for instructions in the instruction stream are defined. The format includes an opcode, an address, and data. The instruction stream is created using the header, the opcode, the address, and the data. The artificial neural network is implemented by providing the instruction stream to a computer processor for execution of the instruction stream.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: October 18, 2022
    Assignee: Raytheon Company
    Inventors: John E. Mixter, David R. Mucha
  • Deep neural network processor with interleaved backpropagation
    Patent number: 11468332
    Abstract: Processing circuitry for a deep neural network can include input/output ports, and a plurality of neural network layers coupled in order from a first layer to a last layer, each of the plurality of neural network layers including a plurality of weighted computational units having circuitry to interleave forward propagation of computational unit input values from the first layer to the last layer and backward propagation of output error values from the last layer to the first layer.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: October 11, 2022
    Assignee: Raytheon Company
    Inventors: John R. Goulding, John E. Mixter, David R. Mucha, Troy A. Gangwer, Ryan D. Silva
  • NEURAL NETWORK INSTRUCTION STREAMING
    Publication number: 20210133579
    Abstract: An artificial neural network is implemented via an instruction stream. A header of the instruction stream and a format for instructions in the instruction stream are defined. The format includes an opcode, an address, and data. The instruction stream is created using the header, the opcode, the address, and the data. The artificial neural network is implemented by providing the instruction stream to a computer processor for execution of the instruction stream.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 6, 2021
    Inventors: John E. Mixter, David R. Mucha
  • Neural network processor with direct memory access and hardware acceleration circuits
    Patent number: 10872290
    Abstract: A dynamically adaptive neural network processing system includes memory to store instructions representing a neural network in contiguous blocks, hardware acceleration (HA) circuitry to execute the neural network, direct memory access (DMA) circuitry to transfer the instructions from the contiguous blocks of the memory to the HA circuitry, and a central processing unit (CPU) to dynamically modify a linked list representing the neural network during execution of the neural network by the HA circuitry to perform machine learning, and to generate the instructions in the contiguous blocks of the memory based on the linked list.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: December 22, 2020
    Assignee: Raytheon Company
    Inventors: John R. Goulding, John E. Mixter, David R. Mucha
  • DEEP NEURAL NETWORK PROCESSOR WITH INTERLEAVED BACKPROPAGATION
    Publication number: 20190147342
    Abstract: Processing circuitry for a deep neural network can include input/output ports, and a plurality of neural network layers coupled in order from a first layer to a last layer, each of the plurality of neural network layers including a plurality of weighted computational units having circuitry to interleave forward propagation of computational unit input values from the first layer to the last layer and backward propagation of output error values from the last layer to the first layer.
    Type: Application
    Filed: November 13, 2017
    Publication date: May 16, 2019
    Inventors: John R. Goulding, John E. Mixter, David R. Mucha, Troy A. Gangwer, Ryan D. Silva
  • NEURAL NETWORK PROCESSOR WITH DIRECT MEMORY ACCESS AND HARDWARE ACCELERATION CIRCUITS
    Publication number: 20190087708
    Abstract: A dynamically adaptive neural network processing system includes memory to store instructions representing a neural network in contiguous blocks, hardware acceleration (HA) circuitry to execute the neural network, direct memory access (DMA) circuitry to transfer the instructions from the contiguous blocks of the memory to the HA circuitry, and a central processing unit (CPU) to dynamically modify a linked list representing the neural network during execution of the neural network by the HA circuitry to perform machine learning, and to generate the instructions in the contiguous blocks of the memory based on the linked list.
    Type: Application
    Filed: September 21, 2017
    Publication date: March 21, 2019
    Inventors: John R. Goulding, John E. Mixter, David R. Mucha