Abstract: An interrupt processor controller (IPC) through which all interprocessor interrupts are routed in a complex integrated circuit. For processors which receive external interrupts, the interrupt processor controller may receive those interrupts and route those as well to the particular processor. The IPC includes interrupt routing logic which determines when a subsequent interrupt will cause an error condition with a previously instigated interrupt that has not been cleared. When such a condition occurs, a bit is set in an error detect register that is coupled to the interrupt routing logic. All of the bits of the error detect register are logically OR'ed, the output of which is routed to a single dedicated pin for indicating an interrupt error condition has occurred. This pin may have its signal routed back into the complex integrated circuit for signaling a trap handler or some other mechanism that an interrupt error condition has occurred.

Abstract: Current mirror amplifiers are disclosed, each having first and second ports that can be interchanged as to which is input port and which is output port in response to an electric control signal. A chopper-stabilized differential amplifier that uses such a switchable current mirror amplifier as a balanced-to-single-ended signal converter for output signals is disclosed, which chopper-stabilized differential amplifier is particularly suited for the integrating amplifier in a delta-sigma analog-to-digital converter.