Abstract: In one embodiment, an ESD protection circuit comprises a switchable current sinking circuit connected to a positive ESD clamp rail voltage, which may be a power supply voltage, and a single trigger control circuit coupled to a control connection of the switchable current sinking circuit. The single trigger control circuit may be configured to couple the control connection of the switchable current sinking circuit to a negative ESD clamp rail voltage, which may be signal ground, during an ESD event occurring on the positive ESD clamp rail connection. In one embodiment, the switchable current sinking circuit is capable of sinking large amounts of current, and the ESD protection circuit is tolerant of rail voltages that exceed the breakdown voltage of semiconductor devices used in constructing the ESD circuit. In one embodiment, the single trigger control circuit is implemented with a single n-well, thereby minimizing the amount of required silicon area during fabrication of the ESD protection circuit.

Abstract: A system, e.g. an integrated circuit or part, may include a plurality of pads, e.g. digital I/O pads, each comprising a physical pad and associated pad circuit. In case of an ESD event affecting one or more of the digital I/O pads, PMOS devices configured in an output buffer section between an I/O pad supply rail and the physical output pad—within their respective pad circuits in the affected digital I/O pads—may all be turned on in response to the ESD event. This may allow the capacitance of each pad, in some cases approximately 3 pF capacitance per pad, to charge up, absorbing the energy of the ESD event and reducing the peak voltage the integrated circuit or part experiences as a result of the ESD event. The reduced peak voltage may be directly correlated with improved ESD performance of the product.

Abstract: A system, e.g. an integrated circuit or part, may include a plurality of pads, e.g. digital I/O pads, each comprising a physical pad and associated pad circuit. In case of an ESD event affecting one or more of the digital I/O pads, PMOS devices configured in an output buffer section between an I/O pad supply rail and the physical output pad—within their respective pad circuits in the affected digital I/O pads—may all be turned on in response to the ESD event. This may allow the capacitance of each pad, in some cases approximately 3 pF capacitance per pad, to charge up, absorbing the energy of the ESD event and reducing the peak voltage the integrated circuit or part experiences as a result of the ESD event. The reduced peak voltage may be directly correlated with improved ESD performance of the product.

Abstract: Disclosed is a circuit for providing an appropriate amount of on-hook loss in a digital loop carder transmission system serving telephone customers. The resistance of the customer loop is measured while the customer is off-hook and an amount of loss is added based on that resistance during the off-hook interval. A predetermined constant loss is then added to the appropriate off-hook loss when the equipment returns to on-hook status.