Abstract: A method and apparatus for decoupling the high order portion of the addend from the multiply result in an FMAC (floating-point multiply accumulate unit) such that the FMAC's datapath width is bounded to "2m+1"-bits, and the maximum width of required adders, shifters and leading bit anticipators is also bounded to "2m+1"-bits. The method and apparatus 1) reduce the necessary chip area for implementing an FMAC, and 2) reduce the length of routing paths through adders and shifters.

Abstract: An apparatus and method are disclosed for regulating power consumption in a digital system of the kind including at least one triggerable functional block that consumes more power when triggered than when not triggered. In an embodiment for use with a digital system that includes a pipeline of such triggerable functional blocks, a state machine sequentially applies trigger pulses to each of the functional blocks in the pipeline whenever the output of an OR gate is asserted. It does so by generating a series of enable signals that are used to gate a clock signal to the trigger inputs of the functional blocks. The state machine includes a series of storage devices having outputs. Outputs of the storage devices are used to provide the enable signals. The inputs of the OR gate are coupled to a start signal that indicates when the functional blocks should be triggered to process data, and also to a dummy start signal that indicates when the functional blocks should be triggered to maintain power consumption.

Abstract: The operation of a pipeline is observed by launching two or more sets of data into the pipeline on consecutive clock cycles. The clock free-runs for as many cycles as it takes the data to propagate through the stages of the pipeline. The output latches of each stage of the pipeline are only sampled when the data of interest is held in each output latch, respectively. Observation may be completely controlled through a standard test access port (TAP). Observation may be accomplished by halting the clock to scan new data in and results out, or with the clock free-running. The inputs to the pipeline may come from test registers or from circuitry which feeds the pipeline during normal operation.