Abstract: Conventional methods using signal test patterns to identify wiring errors are difficult to apply to interfaces encoding information as signal state transitions rather than directly as signal states. A system utilizing excitation of wires with selected transition coded patterns and evaluation of received results is described to identify failed wire connections. This approach may be advantageously used to provide fault detection and redundant path selection in systems incorporating stacked chip interconnections using Through Silicon Vias.

Abstract: Conventional methods using signal test patterns to identify wiring errors are difficult to apply to interfaces encoding information as signal state transitions rather than directly as signal states. A system utilizing excitation of wires with selected transition coded patterns and evaluation of received results is described to identify failed wire connections. This approach may be advantageously used to provide fault detection and redundant path selection in systems incorporating stacked chip interconnections using Through Silicon Vias.

Abstract: Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

Abstract: A system for generating CRC code words associated with data ranging up to w-bytes in width to be communicated over a communications channel includes a first plurality of serially coupled code-generation blocks each for generating a CRC value based on data input to each block, respective blocks of the first plurality configured for receiving data inputs having respective byte widths ranging from 2N+M to 2N?L+M, where N is equal to log2(w), and M is an offset value, and L is a whole number based on a maximum propagation delay criteria; a second plurality of parallel coupled code-generation blocks each for generating a CRC value based on data inputs, respective blocks of the second plurality configured for receiving data having respective byte widths ranging from 2N?L?1+M to 20; and, a device for selecting particular CRC code generation blocks in the first and second pluralities to be included in a CRC calculation based on the data input; wherein any number of data input bytes may be processed.

Abstract: Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

Abstract: Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

Abstract: An automated bit-sliced datapath system generating tool is built so design can be performed at a higher level, and automated generation of the synthesizable HDL representation can be accomplished are disclosed. A method defines datapath system characteristics, defines core/pin rules, and then constructs class-type inference rules that can be used for automatically generating the datapath system. An “orthogonal bundling” technique is used that groups pin by a class, and also by a channel identifier. The class-type inference rule corresponding to each class uses of the following factors to infer appropriate wiring: 1) number and type of pins in the class created by the instantiation of cores by the user; 2) attribute definitions on pins set by library core/pin rules; 3) user selection of “global attributes”; 4) user definition of channel bit order (“link orders”) to imply the order of connection between stages; and 5) user-defined attributes set on pin classes.

Abstract: A system and method for aligning data transferred across circuit boundaries having different clock domains. The system includes a buffer circuit comprising a latch for receiving data clocked in a first clock domain and latching the received data in a second clock domain by one of a first edge of a second clock signal, or a second opposite edge of the second clock signal. The first and second clock signals are of the same frequency but operating out of phase. A control circuit receives the first and second clock signals and determines a phase relationship therebetween. The control circuit generates a control signal based on the determined phase relationship which is implemented for selecting one of a rising edge of the second clock signal, or a falling edge of the second clock signal, for latching action in the second clock domain. Reliable data transfer operation is provided for all possible phase relationships of the first and second clock signals.

Abstract: A system for generating CRC code words associated with data ranging up to w-bytes in width. The system is an iterative approach for providing a CRC calculation circuitry with the CRC calculation being subdivided into a blocks with selectable bus widths which blocks can be cascaded to provide calculation for a parallel bus width of any arbitrary number of bytes. The circuitry includes a first plurality of serially coupled code-generation blocks each for generating a CRC value based on data input to each block; a second plurality of parallel coupled code-generation blocks each for generating a CRC value based on data inputs, and, a device for selecting particular CRC code generation blocks in the first and second pluralities to be included in a CRC calculation based on the data input such that any number of data input bytes may be processed.

Abstract: A system and method that controls the start time of different clocks in different clock domains, each of which is controlling an I/O, provides that the first cycle of each time domain is within a predetermined timing delay of one another. Reset signals are pipelined across the clock domains such that all the clocks trigger at substantially the same time. The clock channels may be arranged logically and physically in n groups of m channels with delays associated with each n group according to the relative position of the n group within the sequence of the n groups.

Abstract: A system for generating CRC code words associated with data ranging up to w-bytes in width to be communicated over a communications channel includes a first plurality of serially coupled code-generation blocks each for generating a CRC value based on data input to each block, respective blocks of the first plurality configured for receiving data inputs having respective byte widths ranging from 2N+M to 2N−L+M, where N is equal to log2 (w), and M is an offset value, and L is a whole number based on a maximum propagation delay criteria; a second plurality of parallel coupled code-generation blocks each for generating a CRC value based on data inputs, respective blocks of the second plurality configured for receiving data having respective byte widths ranging from 2N−L â□□1+M to 20; and, a device for selecting particular CRC code generation blocks in the first and second pluralities to be included in a CRC calculation based on the data input; wherein any number of d

Abstract: A system and method that controls the start time of different clocks in different clock domains, each of which is controlling an I/O, provides that the first cycle of each time domain is within a predetermined timing delay of one another. Reset signals are pipelined across the clock domains such that all the clocks trigger at substantially the same time. The clock channels may be arranged logically and physically in n groups of m channels with delays associated with each n group according to the relative position of the n group within the sequence of the n groups.

Abstract: A History Store Circuit (HSC) is employed with a commercially available FDDI chipset to provide an interface between the PHY layer hardware and a memory system to record symbol stream segments received from the FDDI network. Memory system address and control signals are provided by the HSC. Multiplexor logic is included to support dual-ring network configurations. The HSC provides the electrical interconnection required to interface to the PHY layer hardware so as to allow reception of invalid frames, valid frames, and invalid/valid line state symbol streams from the fiber optic bus. In order to receive such invalid frames and state symbol streams from the fiber optic media, additional logic is provided to allow the user to focus on the segment of network traffic of interest. The HSC includes a Symbol Stream Comparator (SSC) and History Store Triggering Logic (HSTL) to facilitate control of the network traffic segment captured by the HSC.

Abstract: An apparatus for injecting errors into a FDDI token ring network is disclosed. The error injection scheme operates by fooling a FORMAC into thinking it sent a real frame of data. This is done by using two RAM buffers. The RAM buffer normally accessed by the RBC/DPC becomes a SHADOW RAM during error injection operation. A dummy frame is loaded into the shadow RAM in order to fool the FORMAC. This data is just like the data that would be used if sending a normal frame, with the restriction that it must be shorter than the error injection data. The other buffer, the error injection RAM, contains the error injection frame. The error injection data is sent out to the media by switching a multiplexor. When the FORMAC is done transmitting the data, the multiplexor is switched back to the normal mode. Thus, the FORMAC is unaware of what happened and the token ring remains operational.