Patents by Inventor David R. Stiles

David R. Stiles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5515518
    Abstract: AN improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions. The second direct mapped level BPC is a deep but narrow structure (256 2-byte entries), which caches only partial prediction information, but does so for a much larger number of branch instructions. As each branch instruction is fetched and decoded, its address is used to perform parallel look-ups in the two branch prediction caches.
    Type: Grant
    Filed: July 5, 1994
    Date of Patent: May 7, 1996
    Assignee: Nexgen, Inc.
    Inventors: David R. Stiles, John G. Favor, Korbin S. Van Dyke
  • Patent number: 5513330
    Abstract: A method and apparatus for eliminating the delay in a parallel processing pipeline. In a parallel processing pipeline system, a circuitry is provided to determine the length and align two instructions in parallel. Parallel decoding circuitry is provided for decoding and executing the two instructions. A branch prediction cache stores the target instruction and next sequential instruction, and is tagged by the address of the branch instruction, as in the prior art. In addition, however, the branch prediction cache also stores the length of the first and second instructions and the address of the second instruction. This additional data allows the target and next sequential instructions to be directly aligned and presented to the parallel decoding circuits without waiting for a calculation of their lengths and starting addresses.
    Type: Grant
    Filed: October 27, 1993
    Date of Patent: April 30, 1996
    Assignee: NexGen, Inc.
    Inventor: David R. Stiles
  • Patent number: 5511175
    Abstract: The present invention provides for the updating of both the instructions in a branch prediction cache and instructions recently provided to an instruction pipeline from the cache when an instruction being executed attempts to change such instructions ("Store-Into-Instruction-Stream"). The branch prediction cache (BPC) includes a tag identifying the address of instructions causing a branch, a record of the target address which was branched to on the last occurrence of each branch instruction, and a copy of the first several instructions beginning at this target address. A separate instruction cache is provided for normal execution of instructions, and all of the instructions written into the branch prediction cache from the system bus must also be stored in the instruction cache. The instruction cache monitors the system bus for attempts to write to the address of an instruction contained in the instruction cache.
    Type: Grant
    Filed: October 20, 1994
    Date of Patent: April 23, 1996
    Assignee: NexGen, Inc.
    Inventors: John G. Favor, Korbin Van Dyke, David R. Stiles
  • Patent number: 5442757
    Abstract: A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.
    Type: Grant
    Filed: March 3, 1993
    Date of Patent: August 15, 1995
    Assignee: NexGen, Inc.
    Inventors: Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor, Dale R. Greenley, Robert A. Cargnoni
  • Patent number: 5327547
    Abstract: An improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions. The second direct mapped level BPC is a deep but narrow structure (256 2-byte entries), which caches only partial prediction information, but does so for a much larger number of branch instructions. As each branch instruction is fetched and decoded, its address is used to perform parallel look-ups in the two branch prediction caches.
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: July 5, 1994
    Assignee: Nexgen Microsystems
    Inventors: David R. Stiles, John G. Favor, Korbin S. Van Dyke
  • Patent number: 5230068
    Abstract: A system which integrates the multiple instruction queues and the branch target cache (BTC) of a high performance CPU design into a single physical structure. Effectively, the queues are merged into the BTC in such a manner that, at any point in time, most of this structure functions as a BTC while certain entries function as instruction queues.By using parts of the BTC to serve as instruction queues, the inefficiency of separate queue structures is eliminated and the queues are implemented with the greater device density characteristic of the RAM structure which the BTC core is based on. This merging of these structures also substantially simplifies the instruction queue control and the routing of instruction words between BTC entries and queues.
    Type: Grant
    Filed: February 26, 1990
    Date of Patent: July 20, 1993
    Assignee: NexGen Microsystems
    Inventors: Korbin S. Van Dyke, David R. Stiles, John G. Favor
  • Patent number: 5226130
    Abstract: The present invention provides for the updating of both the instructions in a branch prediction cache and instructions recently provided to an instruction pipeline from the cache when an instruction being executed attempts to change such instructions ("Store-Into-Instruction-Stream"). The branch prediction cache (BPC) includes a tag identifying the address of instructions causing a branch, a record of the target address which was branched to on the last occurrence of each branch instruction, and a copy of the first several instructions beginning at this target address. A separate instruction cache is provided for normal execution of instructions, and all of the instructions written into the branch prediction cache from the system bus must also be stored in the instruction cache. The instruction cache monitors the system bus for attempts to write to the address of an instruction contained in the instruction cache.
    Type: Grant
    Filed: February 26, 1990
    Date of Patent: July 6, 1993
    Assignee: NexGen Microsystems
    Inventors: John G. Favor, Korbin Van Dyke, David R. Stiles
  • Patent number: 5226126
    Abstract: A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.
    Type: Grant
    Filed: February 21, 1990
    Date of Patent: July 6, 1993
    Assignee: Nexgen Microsystems
    Inventors: Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor, Dale R. Greenley, Robert A. Cargnoni
  • Patent number: 5163140
    Abstract: An improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions. The second direct mapped level BPC is a deep but narrow structure (256 2-byte entries), which caches only partial prediction information, but does so for a much larger number of branch instructions. As each branch instruction is fetched and decoded, its address is used to perform parallel look-ups in the two branch prediction caches.
    Type: Grant
    Filed: March 2, 1992
    Date of Patent: November 10, 1992
    Assignee: Nexgen Microsystems
    Inventors: David R. Stiles, John G. Favor, Korbin S. Van Dyke
  • Patent number: 5093778
    Abstract: The present invention provides an improved branch prediction cache (BPC) structure that combines various separate structures into one integrated structure. In conjunction with doing this, the present invention is able to share significant portions of hardware cost and design complexity overhead. As a result, the cost-performance trade-off for implementing dynamic branch prediction for target address, branch direction, and target instructions aspects of branches shifts to where "full" branch prediction is now more practical.
    Type: Grant
    Filed: February 26, 1990
    Date of Patent: March 3, 1992
    Assignee: Nexgen Microsystems
    Inventors: John G. Favor, David R. Stiles, Korbin Van Dyke, Walstein B. Smith, III