Patents by Inventor David R. Terry

David R. Terry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10671399
    Abstract: A computer processing system is provided. The computer processing system includes a processor configured to insert a move instruction in an instruction scheduling dependency graph generated for operands of the instruction operating on register pairs to ensure operand readiness for all of the operands used by the instruction operating on register pairs.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Maarten J. Boersma, Sundeep Chadha, Kurt A. Feiste, Michael J. Genden, Michael K. Kroener, David R. Terry
  • Patent number: 10671398
    Abstract: A computer processing system is provided. The computer processing system includes a processor configured to insert a move instruction in an instruction scheduling dependency graph generated for operands of the instruction operating on register pairs to ensure operand readiness for all of the operands used by the instruction operating on register pairs.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Maarten J. Boersma, Sundeep Chadha, Kurt A. Feiste, Michael J. Genden, Michael K. Kroener, David R. Terry
  • Publication number: 20200081713
    Abstract: An approach is provided in which a system writes a set of data into a register file entry that includes a first memory array and a second memory array. The register file entry also includes a set of first write ports corresponding to the first memory array and a set of second write ports corresponding to the second memory array. The system configures a selection bit based on determining that a selected one of the set of first write ports is utilized to store the set of data in the first memory array. In turn, the system reads the set of data out of the first memory array based on the configured selection bit.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 12, 2020
    Inventors: Saiful Islam, Sam G. Chu, Dung Q. Nguyen, Binglong Zhang, Howard Levy, David R. Terry, Steven J. Battle
  • Patent number: 10564691
    Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
  • Patent number: 10545765
    Abstract: Embodiments include systems, methods, and computer program products for using a multi-level history buffer (HB) for a speculative transaction. One method includes after dispatching a first instruction indicating start of the speculative transaction, marking one or more register file (RF) entries as pre-transaction memory (PTM), and after dispatching a second instruction targeting one of the marked RF entries, moving data from the marked RF entry to a first level HB entry and marking the first level HB entry as PTM. The method also includes upon detecting a write back to the first level HB entry, moving data from the first level HB entry to a second level HB entry and marking the second level HB entry as PTM. The method further includes upon determining that the second level HB entry has been completed, moving data from the second level HB entry to a third level HB entry.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, Steven J. Battle, Joshua W. Bowman, Hung Q. Le, Dung Q. Nguyen, David R. Terry, Albert J. Van Norstrand, Jr.
  • Patent number: 10489253
    Abstract: Embodiments include systems, methods, and computer program products for on-demand error detection and correction of registers in a processor. One method includes detecting, before a first instruction is dispatched to an issue queue in the processor, an error in data, associated with the first instruction, stored in an entry of a register file in the processor. The method also includes, after detecting the error, halting the dispatch of the first instruction to the issue queue, and determining whether the entry of the register file has completed. The method further includes determining whether to perform error correction on the register file based on the determination of whether the entry of the register file has completed.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: November 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Battle, Joshua W. Bowman, Sundeep Chadha, Dhivya Jeganathan, Cliff Kucharski, Dung Q. Nguyen, Tu-An T. Nguyen, David R. Terry
  • Patent number: 10379867
    Abstract: Techniques are disclosed for performing a flush and restore of a history buffer (HB) in a processing unit. One technique includes identifying one or more entries of the HB to restore to a register file in the processing unit. For each of the one or more HB entries, a determination is made whether to send the HB entry to the register file via a first restore bus or via a second restore bus, different from the first restore bus, based on contents of the HB entry. Each of the one or more HB entries is then sent to the register file via one of the first restore bus or the second restore bus, based on the determination.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: David R. Terry, Dung Q. Nguyen, Brian W. Thompto, Joshua W. Bowman, Steven J. Battle, Brian D. Barrick, Sundeep Chadha, Albert J. Van Norstrand, Jr.
  • Publication number: 20190213055
    Abstract: Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level transfer of an execution thread between execution slices. Operation of such a multi-slice processor includes responsive to a thread switch signal: halting dispatch of one or more instructions retrieved from an instruction cache; generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice; and dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache; and transferring, in dependence upon execution of the plurality of instructions from the thread switching instruction generator, the execution thread from the first execution slice to the second execution slice.
    Type: Application
    Filed: March 14, 2019
    Publication date: July 11, 2019
    Inventors: BRIAN D. BARRICK, JAMES W. BISHOP, MARCY E. BYERS, SUNDEEP CHADHA, CLIFF KUCHARSKI, DUNG Q. NGUYEN, DAVID R. TERRY, JING ZHANG
  • Publication number: 20190187995
    Abstract: Techniques are disclosed for performing a flush and restore of a history buffer (HB) in a processing unit. One technique inludes identifying one or more entries of the HB to restore to a register file in the processing unit. For each of the one or more HB entries, a determination is made whether to send the HB entry to the register file via a first restore bus or via a second restore bus, different from the first restore bus, based on contents of the HB entry. Each of the one or more HB entries is then sent to the register file via one of the first restore bus or the second restore bus, based on the determination.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 20, 2019
    Inventors: David R. TERRY, Dung Q. NGUYEN, Brian W. THOMPTO, Joshua W. BOWMAN, Steven J. BATTLE, Brian D. BARRICK, Sundeep CHADHA, Albert J. VAN NORSTRAND, JR.
  • Publication number: 20190188133
    Abstract: Techniques are disclosed for performing issue queue snooping for an asynchronous flush and restore of a history buffer (HB) in a processing unit. One technique includes identifying an entry of the HB to restore to a register file in the processing unit. A restore ITAG of the HB entry is sent to the register file via a first restore bus, and restore data of the HB entry and the restore ITAG is sent to the register file via a second restore bus. After the restore ITAG and restore data are sent, an instruction is dispatched before the register file obtains the restore data. After it is determined that the restore data is still available via the second restore bus, a snooping operation is performed to obtain the restore data from the second restore bus for the dispatched instruction.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 20, 2019
    Inventors: David R. TERRY, Dung Q. NGUYEN, Brian W. THOMPTO, Joshua W. BOWMAN, Steven J. BATTLE, Sundeep CHADHA, Brian D. BARRICK, Albert J. VAN NORSTRAND, JR.
  • Patent number: 10318356
    Abstract: Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level transfer of an execution thread between execution slices. Operation of such a multi-slice processor includes responsive to a thread switch signal: halting dispatch of one or more instructions retrieved from an instruction cache; generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice; and dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache; and transferring, in dependence upon execution of the plurality of instructions from the thread switching instruction generator, the execution thread from the first execution slice to the second execution slice.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, James W. Bishop, Marcy E. Byers, Sundeep Chadha, Cliff Kucharski, Dung Q. Nguyen, David R. Terry, Jing Zhang
  • Publication number: 20190160293
    Abstract: A system, such as an IMD system, includes a tissue conductance communication (TCC) transmitter configured to generate a beacon signal by generating a carrier signal and modulating a first property of the carrier signal according to a first type of modulation. The TCC transmitter is configured to generate a data signal subsequent to the beacon signal by generating the carrier signal and modulating a second property of the carrier signal different than the first property according to a second type of modulation different than the first type of modulation.
    Type: Application
    Filed: November 29, 2018
    Publication date: May 30, 2019
    Inventors: James D. REINKE, Joel B. ARTMANN, Michael T. HEMMING, David J. PEICHEL, Jonathan P. ROBERTS, Michael B. TERRY, Eric R. WILLIAMS
  • Patent number: 10296337
    Abstract: Methods and apparatus for preventing premature reads from a general purpose register (GPR) including receiving an instruction comprising a source operand identifying a source GPR entry; setting a read-enabled flag based on a value in a particular entry of a source ready vector; if the read-enabled flag indicates data in the source GPR entry is ready for reading, dispatching the received instruction, including performing a read operation of the data in the source GPR entry; and if the read-enabled flag indicates data in the source GPR entry is not ready for reading, dispatching the received instruction without performing a read operation of the data in the source GPR entry.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
  • Patent number: 10289415
    Abstract: Method and system for restoring results to a register file of a processing unit is provided. An instruction is dispatched in a processing slice of the processing unit, targeting a register file, wherein the processing unit includes two or more processing slices, each processing slice including a corresponding history buffer and at least a portion of a register file. The processing unit evicts previous result data from the register file entry to a history buffer corresponding to the processing slice, by writing new result data into the register file entry, in response to the instruction. The processing unit detects a trigger condition relating to a rollback of the processing unit to a previous state, and restores the previous result data from the history buffer to the register file entry, in response to the trigger.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Susan E. Eisen, Cliff Kucharski, Hung Q. Le, Dung Q. Nguyen, David R. Terry
  • Patent number: 10282207
    Abstract: Operation of a multi-slice processor that includes execution slices and load/store slices coupled via a results bus includes: receiving, by an execution slice, a producer instruction, including: storing, in an entry of an issue queue, the producer instruction; and storing, in a register, an issue queue entry identifier representing the entry of the issue queue in which the producer instruction is stored; receiving, by the execution slice, a source instruction, the source instruction dependent upon the result of the producer instruction, including: storing, in another entry of the issue queue, the source instruction and the issue queue entry identifier of the producer instruction; determining in dependence upon the issue queue entry identifier of the producer instruction that the producer instruction has issued from the issue queue; and responsive to the determination that the producer instruction has issued from the issue queue, issuing the source instruction from the issue queue.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: May 7, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, Sundeep Chadha, Michael J. Genden, Jerry Y. Lu, Dung Q. Nguyen, Nasrin Sultana, David R. Terry, David S. Walder
  • Patent number: 10282205
    Abstract: Method and system for restoring data to a register file of a processing unit are provided. A history buffer entry (HBE) is marked for restoration to a register file entry. Result data and control information is sent from the HBE to an Issue Queue (ISQ). The ISQ issues an instruction for loading the result data into the register file entry based on the control information. A write back operation is performed to restore the result data to the register file entry, in response to issuing of the instruction.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: May 7, 2019
    Assignee: International Business Machines Corporation
    Inventors: Susan E. Eisen, Cliff Kucharski, Hung Q. Le, Dung Q. Nguyen, David R. Terry
  • Patent number: 10268482
    Abstract: Operation of a multi-slice processor that includes execution slices and load/store slices coupled via a results bus includes: receiving, by an execution slice, a producer instruction, including: storing, in an entry of an issue queue, the producer instruction; and storing, in a register, an issue queue entry identifier representing the entry of the issue queue in which the producer instruction is stored; receiving, by the execution slice, a source instruction, the source instruction dependent upon the result of the producer instruction, including: storing, in another entry of the issue queue, the source instruction and the issue queue entry identifier of the producer instruction; determining in dependence upon the issue queue entry identifier of the producer instruction that the producer instruction has issued from the issue queue; and responsive to the determination that the producer instruction has issued from the issue queue, issuing the source instruction from the issue queue.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, Sundeep Chadha, Michael J. Genden, Jerry Y. Lu, Dung Q. Nguyen, Nasrin Sultana, David R. Terry, David S. Walder
  • Patent number: 10255071
    Abstract: Method and system for managing a speculative transaction in a processing unit is provided. The speculative transaction is initiated by dispatching a first instruction indicating start of the speculative transaction. One or more register file (RF) entries are marked as pre-transaction memory (PTM), in response to the initiating. At least one second instruction targeting at least one of the marked RF entries is dispatched, while the transaction is active, wherein the at least one second instruction writes new result data into the at least one RF entry. Previous result data evicted from the at least one RF entry by the new result data, is saved into a history buffer (HB) entry. The HB entry is marked as PTM, in response to the saving, wherein the processing unit, upon detecting a trigger, is rolled back to a state before the initiating the transaction by restoring the previous result data to the at least one RF entry.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Salma Ayub, Susan E. Eisen, Glenn O. Kincaid, Cliff Kucharski, Christopher M. Mueller, Dung Q. Nguyen, David R. Terry
  • Patent number: 10248426
    Abstract: Techniques are disclosed for restoring register data in a processor. In one embodiment, a method includes receiving an instruction to flush one or more general purpose registers (GPRs) in a processor. The method also includes determining history buffer entries of a history buffer to be restored to the one or more GPRs. The method includes creating a mask vector that indicates which history buffer entries will be restored to the one or more GPRs. The method further includes restoring the indicated history buffer entries to the one or more GPRs. As each indicated history buffer entry is restored, the method includes updating the mask vector to indicate which history buffer entries have been restored.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, Steven J. Battle, Joshua W. Bowman, Christopher M. Mueller, Dung Q. Nguyen, David R. Terry, Eula Faye Tolentino, Jing Zhang
  • Patent number: 10248421
    Abstract: Operation of a multi-slice processor that includes execution slices and load/store slices coupled via a results bus, including: for a target instruction targeting a logical register, determining whether an entry in a general purpose register representing the logical register is pending a flush; if the entry in the general purpose register representing the logical register is pending a flush: cancelling the flush in the entry of the general purpose register; storing the target instruction in the entry of the general purpose register representing the logical register, and if an entry in a history buffer targeting the logical register is pending a restore, cancelling the restore for the entry of the history buffer.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Sundeep Chadha, Cliff Kucharski, Dung Q. Nguyen, David R. Terry, Jing Zhang