Patents by Inventor David R Thomas

David R Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6239820
    Abstract: The present invention provides an ink-jet printhead substructure highly thermally efficient and greatly simplified in both the method of manufacture and resulting structure. The printhead substructure of the present invention comprises a resistor formed on an insulated substrate, a single conductive layer that provides both the conductive bonding interconnect pads and the conductive traces for the substructure, a passivation layer and a cavitation barrier. The resistor, passivation layer and cavitation barrier may comprise a single graded layer. The graded thin-film structure provides the resistor, passivation and cavitation barrier components without creating abrupt layer interfaces thereby, improving printhead reliability and durability. Fabrication of the printhead substructure of the present invention requires only two or three lithographic masks and a minimized number of sputter source materials.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: May 29, 2001
    Assignee: Hewlett-Packard Company
    Inventors: Domingo A Figueredo, David R. Thomas, Mark A. Buonanno
  • Patent number: 6153114
    Abstract: The present invention provides an ink-jet printhead substructure highly thermally efficient and greatly simplified in both the method of manufacture and resulting structure. The printhead substructure of the present invention comprises a resistor formed on an insulated substrate, a single conductor layer that provides both the conductive bonding interconnect pads and the conductive traces for the substructure, a passivation layer and a cavitation barrier. The resistor, passivation layer and cavitation barrier may comprise a single graded layer. The graded thin-film structure provides the resistor, passivation and cavitation barrier components without creating abrupt layer interfaces thereby, improving printhead reliability and durability. Fabrication of the printhead substructure of the present invention requires only two or three lithographic masks and a minimized number of sputter source materials.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: November 28, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Domingo A. Figueredo, David R. Thomas, Mark A. Buonanno
  • Patent number: 6126276
    Abstract: A printhead used to eject fluid onto a recording medium has an integrated heat-sink which is used to cool the energy dissipation elements used to propel the fluid from the printhead. The printhead is comprised of a semiconductor substrate that has been processed with thin-film layers. On top of the thin-film layers is an orifice layer that has a pattern of orifices. Fluid feed channels, on the side of the printhead opposite the orifice, supply fluid to the pattern of orifices. Within the thin-film layers are energy dissipating elements which are used to transfer energy to the fluid thereby ejecting fluid from the orifice. The fluid is transferred to the orifice opening through fluid feed slots formed in the thin-film layer adjacent to the energy dissipation elements which is exposed in the fluid feed channel. An integrated heat-sink is attached to the energy dissipation elements to remove heat to the semiconductor substrate and the fluid supply in the fluid feed channel.
    Type: Grant
    Filed: March 2, 1998
    Date of Patent: October 3, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Colin C. Davis, Naoto Kawamura, Timothy Beerling, David R. Thomas, William R. Knight, David Waller, Richard Seaver
  • Patent number: 5883650
    Abstract: The present invention provides an ink-jet printhead substructure highly thermally efficient and greatly simplified in both the method of manufacture and resulting structure. The printhead substructure of the present invention comprises a resistor formed on an insulated substrate, a single conductive layer that provides both the conductive bonding interconnect pads and the conductive traces for the substructure, a passivation layer and a cavitation barrier. The resistor, passivation layer and cavitation barrier may comprise a single graded layer. The graded thin-film structure provides the resistor, passivation and cavitation barrier components without creating abrupt layer interfaces thereby, improving printhead reliability and durability. Fabrication of the printhead substructure of the present invention requires only two or three lithographic masks and a minimized number of sputter source materials.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: March 16, 1999
    Assignee: Hewlett-Packard Company
    Inventors: Domingo A. Figueredo, David R. Thomas, Mark A. Buonanno
  • Patent number: 5595434
    Abstract: A flashlight wand attachment including a wand member having a truncated generally conical portion and an opposing member. The attachment also includes threads for fastening the wand member to the opposing member when the wand member is disposed at one end of a wide portion or lamp housing of a handle member or flashlight, and the opposing member is disposed at an opposite end of the wide portion or lamp housing. Fastening the wand member to the opposing member in this way operably connects the wand attachment to the handle member. The present invention also includes a method of attaching a wand attachment to a flashlight.
    Type: Grant
    Filed: January 17, 1995
    Date of Patent: January 21, 1997
    Inventors: Ricky C. Pasch, David R. Thomas
  • Patent number: 5547604
    Abstract: Siloxane compounds having a smectic liquid crystal phase and the general formula ##STR1## wherein each R=alkyl, alkenyl or aryl, Q represents a monovalent group, for example alkyl, --(CH.sub.2).sub.n OM', a chiral organic group, a dye group, a non-linear optic group or the group --(CH.sub.2).sub.n L, in which L represents a siloxane group, M and M' each represent ##STR2## wherein A is carboxyl, T is CN, F or Cl and p=0 or 1, provided that when T is F or Cl x has a value of at least 2.
    Type: Grant
    Filed: February 10, 1995
    Date of Patent: August 20, 1996
    Assignee: Dow Corning Limited
    Inventors: Harry J. Coles, Jonathon P. Hannington, David R. Thomas
  • Patent number: 5455697
    Abstract: A liquid crystal device wherein the liquid crystal material exhibits a smectic phase and cromprises at least one siloxane compound having the general formula ##STR1## in which R=alkyl, alkenyl or aryl, Q represents a monovalent group, for example alkyl --(CH.sub.2).sub.n OM', a chiral organic group, a dye group, a non-linear optic group or the group --(CH.sub.2).sub.n L in which L represents a siloxane group, M and M' each represent ##STR2## wherein A is carboxyl, T is CN, F or Cl and p=0 or 1, provided that when T is F or Cl x has a value of at least 2.
    Type: Grant
    Filed: January 21, 1994
    Date of Patent: October 3, 1995
    Assignee: Dow Corning Limited
    Inventors: Harry J. Coles, Jonathon P. Hannington, David R. Thomas
  • Patent number: 5383103
    Abstract: A flashlight wand attachment including a wand member having a truncated generally conical portion and an opposing member. The attachment also includes threads for fastening the wand member to the opposing member when the wand member is disposed at one end of a wide portion or lamp housing of a handle member or flashlight, and the opposing member is disposed at an opposite end of the wide portion or lamp housing. Fastening the wand member to the opposing member in this way operably connects the wand attachment to the handle member. The present invention also includes a method of attaching a wand attachment to a flashlight.
    Type: Grant
    Filed: September 21, 1993
    Date of Patent: January 17, 1995
    Inventors: Ricky C. Pasch, David R. Thomas
  • Patent number: 5376830
    Abstract: A slope compensation circuit for use with current-programmed switching DC to DC converters is provided which allows operation of the switching converters in the 1-2 MHz range. The circuit avoids feedback of an output voltage which includes the effects of a partially discharged slope capacitor without adding unnecessary delay by using a switch to bypass the discharging slope capacitor and coupling an input stage of the slope compensation circuit to an output driver. A delay in feeding back the output of the slope compensation circuit is provided to assure that the bypassing switch has settled.
    Type: Grant
    Filed: September 17, 1993
    Date of Patent: December 27, 1994
    Assignee: International Business Machines Corporation
    Inventors: Donald J. Ashley, Michael J. Johnson, David R. Thomas
  • Patent number: 5270424
    Abstract: Process for preparing organosilicon compounds having silicon-bonded groups containing olefinic unsaturation by reaction of a silicon compound having SiH groups with a diene having at least 5 carbon atoms and in which the unsaturation is located at the terminal carbon atoms. The process is carried out in the presence of a catalyst which has been prepared by reacting (i) an inorganic solid having surface reactive groups, (ii) an organosilicom compound having a group reactive with the inorganic solid and a group containing nitrogen and/or sulphur and (iii) a platinum compound or complex PtLb in which L is a ligand.Products have reduced content of isomers resulting from migration of double bond to internal position.
    Type: Grant
    Filed: November 23, 1992
    Date of Patent: December 14, 1993
    Assignee: Dow Corning Limited
    Inventors: Robert A. Drake, Brian J. Griffiths, David R. Thomas
  • Patent number: 4902957
    Abstract: A latch (29) is set by a clock (33) to turn on power switch (FET 5). The latch (29) is reset by high voltage comparator (21), by a 50 percent clock delay (35) and by a low-voltage-to-charging-current comparator (19). The voltage at turn-on is compared with a up-ramping reference (15) until it equals an operating reference (17). A temporary delay (pulse circuit 39 and gate 37) is provided before the low voltage comparison can be effective. The delay prevents response to parasitic effects across the power switch (5). Excess drive is prevented resulting from low output currents and malfunctions, and at turn-on.
    Type: Grant
    Filed: April 27, 1989
    Date of Patent: February 20, 1990
    Assignee: International Business Machines Corporation
    Inventors: John C. Cassani, Mark K. DeMoor, Paul W. Graf, Jonathan J. Hurd, Christopher D. Jones, Stephen F. Newton, David R. Thomas
  • Patent number: 4603399
    Abstract: Data from a patch memory (23) is substituted for that in a system ROM (9) by applying high order addresses to a standard PLA (19) having word lines (FIG. 3, 50a-50p). The address orders are separately applied to EXCLUSIVE OR circuits (27a-27g). The PLA (19) is personalized to activate line (21) at addresses to be substituted and to provide logical zeros to the EXCLUSIVE OR circuits (27a-27g) which change during the patch. Only one word line is required for each continuous patch, which vary in size on a patch-by-patch basis. The circuit is fast and efficient. It can be used for a wide variety of memory substitution applications.
    Type: Grant
    Filed: December 27, 1983
    Date of Patent: July 29, 1986
    Assignee: International Business Machines Corporation
    Inventors: Elbert A. Cheek, David R. Thomas, John D. Zbrozek
  • Patent number: 4534017
    Abstract: In response to a periodic pulse on a lead (21) an FET (47) connected gate-to-drain is driven in a low current circuit, producing a threshold potential on node F. This is connected through switch FETs (61) to the word lines (1) of a memory. This holds the gates of memory access switches (5) at threshold. A higher voltage on the bit line (7) takes off charge in memory cells (40) which have drifted from zero charge stored toward the substrate voltage. Absence of the periodic signal activates an FET (59) which grounds node F. High voltage applied to a word line (1) switches off the FET (61) connecting that line to node F.
    Type: Grant
    Filed: October 29, 1981
    Date of Patent: August 6, 1985
    Assignee: International Business Machines Corporation
    Inventors: David R. Thomas, Paul C. Tien