Patents by Inventor David R. Tipple
David R. Tipple has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10192885Abstract: A semiconductor device includes a bulk substrate of a first conductivity type, a first semiconductor on insulator (SOI) block in the bulk substrate, a first well of the first conductivity type in the first SOI block, a second well of a second conductivity type in the first SOI block, a first guard ring of the first conductivity type in the first SOI block around at least a portion of a periphery of the first SOI block, and a second guard ring of the second conductivity type in the first SOI block around at least a portion of the periphery of the first SOI block. The first conductivity type is different than the second conductivity type.Type: GrantFiled: July 31, 2017Date of Patent: January 29, 2019Assignee: NXP USA, Inc.Inventors: Chi-Min Yuan, David R. Tipple
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Patent number: 10094873Abstract: A wafer structure has a plurality of semiconductor die. Each semiconductor die includes circuitry, a test pad for use in testing the circuitry, and a plurality of external pins. The test pad includes first, second, third, and fourth metal lines, a via, and a metal cover that receives a probe. The first and second metal lines are in a first metal layer and run in parallel, are insulated from each other, and are adjacent. The third and fourth metal lines are in a second metal layer run in parallel, are insulated from each other, and run orthogonal to the first and second metal lines. The first via is coupled to the first metal line and the third metal line. One or more external pins are connected to the metal cover.Type: GrantFiled: August 28, 2015Date of Patent: October 9, 2018Assignee: NXP USA, Inc.Inventors: David R. Tipple, Alistair J. Gorman, Anis M. Jarrar
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Publication number: 20170330899Abstract: A semiconductor device includes a bulk substrate of a first conductivity type, a first semiconductor on insulator (SOI) block in the bulk substrate, a first well of the first conductivity type in the first SOI block, a second well of a second conductivity type in the first SOI block, a first guard ring of the first conductivity type in the first SOI block around at least a portion of a periphery of the first SOI block, and a second guard ring of the second conductivity type in the first SOI block around at least a portion of the periphery of the first SOI block. The first conductivity type is different than the second conductivity type.Type: ApplicationFiled: July 31, 2017Publication date: November 16, 2017Inventors: CHI-MIN YUAN, DAVID R. TIPPLE
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Patent number: 9806019Abstract: An integrated circuit includes a first transistor including a first current electrode, a second current electrode, and a bulk tie; a first conductive line coupled between the first current electrode and a first supply voltage; and a second conductive line coupled to the second current electrode. A resistance of the second conductive line is at least 5 percent greater than a resistance of the first conductive line. The bulk tie is coupled to a second supply voltage. The first supply voltage is different than the second supply voltage.Type: GrantFiled: September 22, 2015Date of Patent: October 31, 2017Assignee: NXP USA, Inc.Inventors: Anis M. Jarrar, David R. Tipple, Jeff L. Warner
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Patent number: 9754966Abstract: A semiconductor device includes a bulk substrate of a first conductivity type, a first semiconductor on insulator (SOI) block in the bulk substrate, a first well of the first conductivity type in the first SOI block, a second well of a second conductivity type in the first SOI block, a first guard ring of the first conductivity type in the first SOI block around at least a portion of a periphery of the first SOI block, and a second guard ring of the second conductivity type in the first SOI block around at least a portion of the periphery of the first SOI block. The first conductivity type is different than the second conductivity type.Type: GrantFiled: April 26, 2016Date of Patent: September 5, 2017Assignee: NXP USA, Inc.Inventors: Chi-Min Yuan, David R. Tipple
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Publication number: 20170084535Abstract: An integrated circuit includes a first transistor including a first current electrode, a second current electrode, and a bulk tie; a first conductive line coupled between the first current electrode and a first supply voltage; and a second conductive line coupled to the second current electrode. A resistance of the second conductive line is at least 5 percent greater than a resistance of the first conductive line. The bulk tie is coupled to a second supply voltage. The first supply voltage is different than the second supply voltage.Type: ApplicationFiled: September 22, 2015Publication date: March 23, 2017Inventors: ANIS M. JARRAR, DAVID R. TIPPLE, JEFF L. WARNER
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Publication number: 20170059650Abstract: A wafer structure has a plurality of semiconductor die. Each semiconductor die includes circuitry, a test pad for use in testing the circuitry, and a plurality of external pins. The test pad includes first, second, third, and fourth metal lines, a via, and a metal cover that receives a probe. The first and second metal lines are in a first metal layer and run in parallel, are insulated from each other, and are adjacent. The third and fourth metal lines are in a second metal layer run in parallel, are insulated from each other, and run orthogonal to the first and second metal lines. The first via is coupled to the first metal line and the third metal line. One or more external pins are connected to the metal cover.Type: ApplicationFiled: August 28, 2015Publication date: March 2, 2017Inventors: David R. Tipple, Alistair J. Gorman, Anis M. Jarrar
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Patent number: 9438242Abstract: A method of making a first timing path includes developing a first design of the first timing path with a first logic circuit and a first functional cell, wherein the first functional cell comprises a first transistor that is spaced from a first well boundary. The timing path is analyzed to determine if the first timing path has positive timing slack. If the analyzed speed of operation shows positive timing slack, the design is changed to a modified design to reduce power consumption of the first timing path by moving the first transistor closer to the first well boundary. Also the first timing path is then built using the modified design to reduce power consumption of the first timing path by reducing leakage power consumption of the first transistor.Type: GrantFiled: July 12, 2013Date of Patent: September 6, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Anis M. Jarrar, Mark D. Hall, David R. Tipple, Surya Veeraraghavan
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Publication number: 20160065185Abstract: A processing system includes a processor core, a peripheral component, and a flip-flop unit in at least one of the processor core and the peripheral component. The flip-flop unit can include a master latch, and two slave latches coupled to an output of the master latch. The first slave latch is formed over a first doped well region of a semiconductor substrate. The second slave latch is formed over a second doped well region of the semiconductor substrate. A comparator is coupled to an output of the first slave latch and to an output of the second slave latch. An output of the comparator indicates whether a state stored in the first slave latch is the same as a state stored in the second slave latch.Type: ApplicationFiled: August 29, 2014Publication date: March 3, 2016Inventors: Anis M. Jarrar, John M. Boyer, Saji George, David R. Tipple
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Patent number: 9264021Abstract: A processing system includes a processor core, a peripheral component, and a flip-flop unit in at least one of the processor core and the peripheral component. The flip-flop unit can include a master latch, and two slave latches coupled to an output of the master latch. The first slave latch is formed over a first doped well region of a semiconductor substrate. The second slave latch is formed over a second doped well region of the semiconductor substrate. A comparator is coupled to an output of the first slave latch and to an output of the second slave latch. An output of the comparator indicates whether a state stored in the first slave latch is the same as a state stored in the second slave latch.Type: GrantFiled: August 29, 2014Date of Patent: February 16, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Anis M. Jarrar, John M. Boyer, Saji George, David R. Tipple
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Publication number: 20150015306Abstract: A method of making a first timing path includes developing a first design of the first timing path with a first logic circuit and a first functional cell, wherein the first functional cell comprises a first transistor that is spaced from a first well boundary. The timing path is analyzed to determine if the first timing path has positive timing slack. If the analyzed speed of operation shows positive timing slack, the design is changed to a modified design to reduce power consumption of the first timing path by moving the first transistor closer to the first well boundary. Also the first timing path is then built using the modified design to reduce power consumption of the first timing path by reducing leakage power consumption of the first transistor.Type: ApplicationFiled: July 12, 2013Publication date: January 15, 2015Inventors: Anis M. Jarrar, Mark D. Hall, David R. Tipple, Surya Veeraraghavan
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Patent number: 7868877Abstract: A touch panel detection circuit includes current limiting circuitry that has a first portion coupled between a first supply voltage terminal and a first input node and a second portion coupled between a second input node and a second supply voltage terminal. Programmable precharge circuitry connects the first input node to the first supply voltage terminal via a conductive path that is in parallel with the first portion of the current limiting circuitry and precharges the first input node to a predetermined voltage. Comparison circuitry is coupled to the programmable precharge circuitry and to the first input node. The comparison circuitry detects a change in resistance between the first input node and the second input node and provides a signal in response thereto when the comparison circuitry is enabled by the programmable precharge circuitry.Type: GrantFiled: October 18, 2007Date of Patent: January 11, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Stefano Pietri, Sheng Lin, Alfredo Olmos, David R. Tipple
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Publication number: 20090102802Abstract: A touch panel detection circuit includes current limiting circuitry that has a first portion coupled between a first supply voltage terminal and a first input node and a second portion coupled between a second input node and a second supply voltage terminal. Programmable precharge circuitry connects the first input node to the first supply voltage terminal via a conductive path that is in parallel with the first portion of the current limiting circuitry and precharges the first input node to a predetermined voltage. Comparison circuitry is coupled to the programmable precharge circuitry and to the first input node. The comparison circuitry detects a change in resistance between the first input node and the second input node and provides a signal in response thereto when the comparison circuitry is enabled by the programmable precharge circuitry.Type: ApplicationFiled: October 18, 2007Publication date: April 23, 2009Inventors: Stefano Pietri, Sheng Lin, Alfredo Olmos, David R. Tipple
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Patent number: 5751978Abstract: An output driver (10) for a bus interface and associated method of operation. The output driver (10) comprises a first driver circuit (12), a second driver circuit (14), and a controller (16). The first driver circuit (12) provides data at a first current level to an output (18) while the second driver circuit (14) provides data to the output (18) at a second current level when activated. The controller (16), by selectively operating the first driver circuit (12) and the second driver circuit (14) causes the output driver (10) to selectively operate in differing modes of operation over time. In this fashion, the output driver (10) operates in Classical Mode (84), Active Negate Mode (80), Pulsed Negation Mode (82), and Differential Mode (86) based upon the requirements of peripheral devices (106, 108. 110. 112) and peripheral bus (20) requirements.Type: GrantFiled: November 13, 1995Date of Patent: May 12, 1998Assignee: Motorola, Inc.Inventor: David R. Tipple