Abstract: The present invention provides an adaptive keeper circuit to control Domino Logic Dynamic Circuits using Rate Sensing Technique to provide reduced contention and efficient process tracking at given noise robustness with less overhead in area, power and delay, said adaptive keeper comprising, keeper PMOS transistor (M1), wherein the drain of M1 is connected to wide AND-OR logic circuit; the rate controller consisting of reference rate transistor (M4), feedback PMOS transistor (M2), feedback shutoff transistor (M5), clock shutoff transistor (M6), pre-charge PMOS transistor (M3), wherein the input of the rate controller is directly connected to drain of the keeper PMOS (M1) and the output of the rate controller is directly connected to the gate of the PMOS keeper (M1).

Abstract: The present invention provides an adaptive keeper circuit to control Domino Logic Dynamic Circuits using Rate Sensing Technique to provide reduced contention and efficient process tracking at given noise robustness with less overhead in area, power and delay, said adaptive keeper comprising, keeper PMOS transistor (M1), wherein the drain of M1 is connected to wide AND-OR logic circuit; the rate controller consisting of reference rate transistor (M4), feedback PMOS transistor (M2), feed-back shutoff transistor (M5), clock shutoff transistor (M6), pre-charge PMOS transistor (M3), wherein the input of the rate controller is directly connected to drain of the keeper PMOS (M1) and the output of the rate controller is directly connected to the gate of the PMOS keeper (M1),