Patents by Inventor David Rath

David Rath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100287608
    Abstract: The invention provides an improved network and methods of operation thereof for use in or with process control systems, computer-based manufacturing or production control systems, environmental control systems, industrial control system, and the like (collectively, “control systems”). Those networks utilize a unique combination of firewalls, intrusion detection systems, intrusion protection devices and/or other devices for hardening (e.g., security against hacking, intrusion or other mischievous conduct) and/or intrusion detection. The networks and methods have application, by way of example, in plants, sites and other facilities in which networks that support control systems interface with corporate, business or other networks.
    Type: Application
    Filed: April 16, 2010
    Publication date: November 11, 2010
    Applicant: INVENSYS SYSTEMS, INC.
    Inventors: Bharat Khuti, Clayton Coleman, David Rath, Ernest Rakaczky, Jim Leslie, Juan Peralta, George Simpson
  • Patent number: 7761923
    Abstract: The invention provides an improved network and methods of operation thereof for use in or with process control systems, computer-based manufacturing or production control systems, environmental control systems, industrial control system, and the like (collectively, “control systems”). Those networks utilize a unique combination of firewalls, intrusion detection systems, intrusion protection devices and/or other devices for hardening (e.g., security against hacking, intrusion or other mischievous conduct) and/or intrusion detection. The networks and methods have application, by way of example, in plants, sites and other facilities in which networks that support control systems interface with corporate, business or other networks.
    Type: Grant
    Filed: March 1, 2005
    Date of Patent: July 20, 2010
    Assignee: Invensys Systems, Inc.
    Inventors: Bharat Khuti, Clayton Coleman, David Rath, Ernest Rakaczky, Jim Leslie, Juan Peralta, George Simpson
  • Patent number: 7614083
    Abstract: The invention provides an improved network and methods of operation thereof for use in or with process control systems, computer-based manufacturing or production control systems, environmental control systems, industrial control system, and the like (collectively, “control systems”). Those networks utilize a unique combination of firewalls, intrusion detection systems, intrusion protection devices and/or other devices for hardening (e.g., security against hacking, intrusion or other mischievous conduct) and/or intrusion detection. The networks and methods have application, by way of example, in plants, sites and other facilities in which networks that support control systems interface with corporate, business or other networks.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: November 3, 2009
    Assignee: Invensys Systems, Inc.
    Inventors: Bharat Khuti, Clayton Coleman, David Rath, Ernest Rakaczky, Jim Leslie, Juan Peralta, George Simpson
  • Publication number: 20080284019
    Abstract: A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating seed layer in the via; reducing the thickness of the sacrificial seed layer by reverse plating; and plating a conductive metal on the sacrificial seed layer in the patterned feature. Also provided is a dielectric layer having a via therein; a plating seed layer on the dielectric layer in the patterned feature; and a discontinuous sacrificial seed layer located in the patterned feature.
    Type: Application
    Filed: May 29, 2008
    Publication date: November 20, 2008
    Applicant: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Shom Ponoth, David Rath, Keith Kwong Hon Wong
  • Patent number: 7446036
    Abstract: A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: November 4, 2008
    Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc.
    Inventors: Tibor Bolom, Stephan Grunow, David Rath, Andrew Herbert Simon
  • Publication number: 20080012142
    Abstract: Methods are provided that enable the ability to use a less aggressive liner processes, while producing structures known to give a desired high stress migration and electro-migration reliability. The present invention circumvents the issue of sputter damage of low k (on the order of 3.2 or less) dielectric by creating the via “anchors” (interlocked and interpenetrated vias) through chemical means. This allows the elimination or significant reduction of the sputter-etching process used to create the via penetration (“drilling, gouging”) into the line below in the barrier/seed metallization step. The present invention achieves the above, while maintaining a reliable copper fill and device structure.
    Type: Application
    Filed: February 15, 2006
    Publication date: January 17, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sanjay Mehta, Daniel Edelstein, John Fitzsimmons, Stephan Grunow, Henry Nye, David Rath
  • Publication number: 20070117377
    Abstract: A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating seed layer in the via; reducing the thickness of the sacrificial seed layer by reverse plating; and plating a conductive metal on the sacrificial seed layer in the patterned feature. Also provided is a dielectric layer having a via therein; a plating seed layer on the dielectric layer in the patterned feature; and a discontinuous sacrificial seed layer located in the patterned feature.
    Type: Application
    Filed: November 23, 2005
    Publication date: May 24, 2007
    Inventors: Chih-Chao Yang, Shom Ponoth, David Rath, Keith Wong
  • Publication number: 20070059922
    Abstract: The present invention relates to methods for post-etch, particularly post-RIE, removal of fluorocarbon-based residues from a hybrid dielectric structure. The hybrid dielectric structure contains a first dielectric material, and a line-level dielectric layer containing a second, different dielectric material, and wherein said second, different dielectric material comprises a polymeric thermoset dielectric material having a dielectric constant less than 4. Low energy electron beam or low temperature annealing is utilized by the present invention for removal of the fluorocarbon-based residues from such a hybrid dielectric structure, without damaging the low-k polymeric thermoset dielectric material contained in such a hybrid dielectric structure.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 15, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence Clevenger, Andrew Cowley, Timothy Dalton, Mark Hoinkis, Kaushik Kumar, Douglas La Tulipe, David Rath, Chih-Chao Yang
  • Publication number: 20060294579
    Abstract: The invention provides an improved network and methods of operation thereof for use in or with process control systems, computer-based manufacturing or production control systems, environmental control systems, industrial control system, and the like (collectively, “control systems”). Those networks utilize a unique combination of firewalls, intrusion detection systems, intrusion protection devices and/or other devices for hardening (e.g., security against hacking, intrusion or other mischievous conduct) and/or intrusion detection. The networks and methods have application, by way of example, in plants, sites and other facilities in which networks that support control systems interface with corporate, business or other networks.
    Type: Application
    Filed: March 1, 2005
    Publication date: December 28, 2006
    Applicant: INVENSYS SYSTEMS, INC.
    Inventors: Bharat Khuti, Clayton Coleman, David Rath, Ernest Rahaczky, Jim Leslie, Juan Peralta, George Simpson
  • Publication number: 20060183056
    Abstract: Copper and copper alloys are etched to provide uniform and smooth surface by employing an aqueous composition that comprises an oxidant, a mixture of at least one weak complexant and at least one strong complexant for the copper or copper alloy, and water and has a pH of about 6 to about 12 so as to form an oxidized etch controlling layer and to uniformly remove the copper or copper alloy; and then removing the oxidized etch controlling layer with a non-oxidizing composition. Copper and copper alloy structure, having smooth upper surfaces are also provided.
    Type: Application
    Filed: April 12, 2006
    Publication date: August 17, 2006
    Applicant: International Business Machines Corporation
    Inventors: Emanuel Cooper, Bruce Furman, David Rath
  • Patent number: 7056648
    Abstract: Copper and copper alloys are etched to provide uniform and smooth surface by employing an aqueous composition that comprises an oxidant, a mixture of at least one weak complexant and at least one strong complexant for the copper or copper alloy, and water and has a pH of about 6 to about 12 so as to form an oxidized etch controlling layer and to uniformly remove the copper or copper alloy; and then removing the oxidized etch controlling layer with a non-oxidizing composition. Copper and copper alloy structure, having smooth upper surfaces are also provided.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: June 6, 2006
    Assignee: International Business Machines Corporation
    Inventors: Emanuel Cooper, Bruce Furman, David Rath
  • Publication number: 20060089000
    Abstract: In the back end of integrated circuits employing low-k interlevel dielectrics, etched structures are filled with a planarizing material comprising a cyclic olefin polymer and solvent; the next pattern to be etched is defined in a photosensitive layer above the planarizing layer; the pattern is etched in the dielectric and the planarizing material is stripped in a wet process that does not damage the interlevel dielectric.
    Type: Application
    Filed: October 26, 2004
    Publication date: April 27, 2006
    Applicant: International Business Machines Corporation
    Inventors: Ronald Della Guardia, Ranee Kwong, Wenjie Li, Qinghuang Lin, Dirk Pfeiffer, David Rath
  • Publication number: 20060053491
    Abstract: The invention provides an improved network and methods of operation thereof for use in or with process control systems, computer-based manufacturing or production control systems, environmental control systems, industrial control system, and the like (collectively, “control systems”). Those networks utilize a unique combination of firewalls, intrusion detection systems, intrusion protection devices and/or other devices for hardening (e.g., security against hacking, intrusion or other mischievous conduct) and/or intrusion detection. The networks and methods have application, by way of example, in plants, sites and other facilities in which networks that support control systems interface with corporate, business or other networks.
    Type: Application
    Filed: March 11, 2005
    Publication date: March 9, 2006
    Applicant: INVENSYS SYSTEMS, INC.
    Inventors: Bharat Khuti, Clayton Coleman, David Rath, Ernest Rakaczky, Jim Leslie, Juan Peralta, George Simpson
  • Publication number: 20060043590
    Abstract: A chemical mechanical polishing (CMP) step is used to remove excess conductive material (e.g., Cu) overlying a low-k or ultralow-k interlevel dielectric layer (ILD) layer having trenches filled with conductive material, for a damascene interconnect structure. A reactive ion etch (RIE) or a Gas Cluster Ion Beam (GCIB) process is used to remove a portion of a liner which is atop a hard mask. A wet etch step is used to remove an oxide portion of the hard mask overlying the ILD, followed by a final touch-up Cu CMP (CMP) step which chops the protruding Cu patterns off and lands on the SiCOH hard mask. In this manner, processes used to remove excess conductive material substantially do not affect the portion of the hard mask overlying the interlevel dielectric layer.
    Type: Application
    Filed: August 27, 2004
    Publication date: March 2, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven Shyng-Tsong Chen, Kaushik Kumar, Stephen Greco, Shom Ponoth, Terry Spooner, David Rath, Wei-Tsu Tseng
  • Publication number: 20050158985
    Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.
    Type: Application
    Filed: February 16, 2005
    Publication date: July 21, 2005
    Inventors: Shyng-Tsong Chen, Timothy Dalton, Kenneth Davis, Chao-Kun Hu, Fen Jamin, Steffen Kaldor, Mahadevaiyer Krishnan, Kaushik Kumar, Michael Lofaro, Sandra Malhotra, Chandrasekhar Narayan, David Rath, Judith Rubino, Katherine Saenger, Andrew Simon, Sean Smith, Wei-tsu Tseng
  • Publication number: 20050081884
    Abstract: The present invention provides a method cleaning of semiconductor devices through heterogeneous nucleation of cavitation bubbles. Heterogeneous nucleation is performed by applying sonic energy to a cleaning solution and a phase material in order to remove unwanted particles from semiconductor devices. A surfactant may be added to the phase material and the cleaning solution.
    Type: Application
    Filed: October 15, 2003
    Publication date: April 21, 2005
    Applicants: Infineon Technologies North America Corp., International Business Machines Corporation
    Inventors: Ravikumar Ramachandran, David Rath
  • Publication number: 20050056616
    Abstract: Copper and copper alloys are etched to provide uniform and smooth surface by employing an aqueous composition that comprises an oxidant, a mixture of at least one weak complexant and at least one strong complexant for the copper or copper alloy, and water and has a pH of about 6 to about 12 so as to form an oxidized etch controlling layer and to uniformly remove the copper or copper alloy; and then removing the oxidized etch controlling layer with a non-oxidizing composition. Copper and copper alloy structure, having smooth upper surfaces are also provided.
    Type: Application
    Filed: September 17, 2003
    Publication date: March 17, 2005
    Applicant: International Business Machines Corporation
    Inventors: Emanuel Cooper, Bruce Furman, David Rath
  • Patent number: 6295998
    Abstract: A system is provided to prepare deionized water having a 100% saturated concentration of a gas, e.g., nitrogen, at a hot temperature, e.g., 50-85° C., and an attendant pressure, e.g., atmospheric pressure, to clean a semiconductor wafer, e.g., of silicon. The gas concentration of a first deionized water portion having a predetermined concentration of the gas at a cold temperature, e.g., 20-30° C., is adjusted in a gassifier chamber having a pressure pump and a pressure sensor, to provide a predetermined under-saturated concentration of the gas at the cold temperature. The temperature of the adjusted gas concentration first water portion is then adjusted by mixing therewith a second deionized water portion having a predetermined concentration of the gas at a predetermined very hot temperature, e.g., 80° C., in a predetermined ratio in a mixer having a temperature sensor.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: October 2, 2001
    Assignees: Infineon Technologies North America Corp., International Business Machines Corporation
    Inventors: Stephan Kudelka, David Rath
  • Patent number: 6167891
    Abstract: A system is provided to prepare deionized water having a 100% saturated concentration of a gas, e.g., nitrogen, at a hot temperature, e.g., 50-85° C., and an attendant pressure, e.g., atmospheric pressure, to clean a semiconductor wafer, e.g., of silicon. The gas concentration of deionized water having a predetermined concentration of the gas at a cold temperature, e.g., 15-30° C., is adjusted in a degassifier chamber having a vacuum pump and a pressure sensor, to provide an under-saturated concentration of the gas at the cold temperature corresponding to the saturated concentration thereof at the hot temperature and attendant pressure. The adjusted gas concentration water is then heated in a heating vessel having a heater and a temperature sensor, to the hot temperature to form a hot bath having such saturated gas concentration to clean the wafer, e.g., in a cleaning tank under megasonic vibrations.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: January 2, 2001
    Assignee: Infineon Technologies North America Corp.
    Inventors: Stephan Kudelka, David Rath