Patents by Inventor David Rath
David Rath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100287608Abstract: The invention provides an improved network and methods of operation thereof for use in or with process control systems, computer-based manufacturing or production control systems, environmental control systems, industrial control system, and the like (collectively, “control systems”). Those networks utilize a unique combination of firewalls, intrusion detection systems, intrusion protection devices and/or other devices for hardening (e.g., security against hacking, intrusion or other mischievous conduct) and/or intrusion detection. The networks and methods have application, by way of example, in plants, sites and other facilities in which networks that support control systems interface with corporate, business or other networks.Type: ApplicationFiled: April 16, 2010Publication date: November 11, 2010Applicant: INVENSYS SYSTEMS, INC.Inventors: Bharat Khuti, Clayton Coleman, David Rath, Ernest Rakaczky, Jim Leslie, Juan Peralta, George Simpson
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Patent number: 7761923Abstract: The invention provides an improved network and methods of operation thereof for use in or with process control systems, computer-based manufacturing or production control systems, environmental control systems, industrial control system, and the like (collectively, “control systems”). Those networks utilize a unique combination of firewalls, intrusion detection systems, intrusion protection devices and/or other devices for hardening (e.g., security against hacking, intrusion or other mischievous conduct) and/or intrusion detection. The networks and methods have application, by way of example, in plants, sites and other facilities in which networks that support control systems interface with corporate, business or other networks.Type: GrantFiled: March 1, 2005Date of Patent: July 20, 2010Assignee: Invensys Systems, Inc.Inventors: Bharat Khuti, Clayton Coleman, David Rath, Ernest Rakaczky, Jim Leslie, Juan Peralta, George Simpson
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Patent number: 7614083Abstract: The invention provides an improved network and methods of operation thereof for use in or with process control systems, computer-based manufacturing or production control systems, environmental control systems, industrial control system, and the like (collectively, “control systems”). Those networks utilize a unique combination of firewalls, intrusion detection systems, intrusion protection devices and/or other devices for hardening (e.g., security against hacking, intrusion or other mischievous conduct) and/or intrusion detection. The networks and methods have application, by way of example, in plants, sites and other facilities in which networks that support control systems interface with corporate, business or other networks.Type: GrantFiled: March 11, 2005Date of Patent: November 3, 2009Assignee: Invensys Systems, Inc.Inventors: Bharat Khuti, Clayton Coleman, David Rath, Ernest Rakaczky, Jim Leslie, Juan Peralta, George Simpson
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Publication number: 20080284019Abstract: A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating seed layer in the via; reducing the thickness of the sacrificial seed layer by reverse plating; and plating a conductive metal on the sacrificial seed layer in the patterned feature. Also provided is a dielectric layer having a via therein; a plating seed layer on the dielectric layer in the patterned feature; and a discontinuous sacrificial seed layer located in the patterned feature.Type: ApplicationFiled: May 29, 2008Publication date: November 20, 2008Applicant: International Business Machines CorporationInventors: Chih-Chao Yang, Shom Ponoth, David Rath, Keith Kwong Hon Wong
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Patent number: 7446036Abstract: A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids.Type: GrantFiled: December 18, 2007Date of Patent: November 4, 2008Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc.Inventors: Tibor Bolom, Stephan Grunow, David Rath, Andrew Herbert Simon
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Publication number: 20080012142Abstract: Methods are provided that enable the ability to use a less aggressive liner processes, while producing structures known to give a desired high stress migration and electro-migration reliability. The present invention circumvents the issue of sputter damage of low k (on the order of 3.2 or less) dielectric by creating the via “anchors” (interlocked and interpenetrated vias) through chemical means. This allows the elimination or significant reduction of the sputter-etching process used to create the via penetration (“drilling, gouging”) into the line below in the barrier/seed metallization step. The present invention achieves the above, while maintaining a reliable copper fill and device structure.Type: ApplicationFiled: February 15, 2006Publication date: January 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sanjay Mehta, Daniel Edelstein, John Fitzsimmons, Stephan Grunow, Henry Nye, David Rath
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Publication number: 20070117377Abstract: A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating seed layer in the via; reducing the thickness of the sacrificial seed layer by reverse plating; and plating a conductive metal on the sacrificial seed layer in the patterned feature. Also provided is a dielectric layer having a via therein; a plating seed layer on the dielectric layer in the patterned feature; and a discontinuous sacrificial seed layer located in the patterned feature.Type: ApplicationFiled: November 23, 2005Publication date: May 24, 2007Inventors: Chih-Chao Yang, Shom Ponoth, David Rath, Keith Wong
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Publication number: 20070059922Abstract: The present invention relates to methods for post-etch, particularly post-RIE, removal of fluorocarbon-based residues from a hybrid dielectric structure. The hybrid dielectric structure contains a first dielectric material, and a line-level dielectric layer containing a second, different dielectric material, and wherein said second, different dielectric material comprises a polymeric thermoset dielectric material having a dielectric constant less than 4. Low energy electron beam or low temperature annealing is utilized by the present invention for removal of the fluorocarbon-based residues from such a hybrid dielectric structure, without damaging the low-k polymeric thermoset dielectric material contained in such a hybrid dielectric structure.Type: ApplicationFiled: September 13, 2005Publication date: March 15, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence Clevenger, Andrew Cowley, Timothy Dalton, Mark Hoinkis, Kaushik Kumar, Douglas La Tulipe, David Rath, Chih-Chao Yang
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Publication number: 20060294579Abstract: The invention provides an improved network and methods of operation thereof for use in or with process control systems, computer-based manufacturing or production control systems, environmental control systems, industrial control system, and the like (collectively, “control systems”). Those networks utilize a unique combination of firewalls, intrusion detection systems, intrusion protection devices and/or other devices for hardening (e.g., security against hacking, intrusion or other mischievous conduct) and/or intrusion detection. The networks and methods have application, by way of example, in plants, sites and other facilities in which networks that support control systems interface with corporate, business or other networks.Type: ApplicationFiled: March 1, 2005Publication date: December 28, 2006Applicant: INVENSYS SYSTEMS, INC.Inventors: Bharat Khuti, Clayton Coleman, David Rath, Ernest Rahaczky, Jim Leslie, Juan Peralta, George Simpson
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Publication number: 20060183056Abstract: Copper and copper alloys are etched to provide uniform and smooth surface by employing an aqueous composition that comprises an oxidant, a mixture of at least one weak complexant and at least one strong complexant for the copper or copper alloy, and water and has a pH of about 6 to about 12 so as to form an oxidized etch controlling layer and to uniformly remove the copper or copper alloy; and then removing the oxidized etch controlling layer with a non-oxidizing composition. Copper and copper alloy structure, having smooth upper surfaces are also provided.Type: ApplicationFiled: April 12, 2006Publication date: August 17, 2006Applicant: International Business Machines CorporationInventors: Emanuel Cooper, Bruce Furman, David Rath
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Patent number: 7056648Abstract: Copper and copper alloys are etched to provide uniform and smooth surface by employing an aqueous composition that comprises an oxidant, a mixture of at least one weak complexant and at least one strong complexant for the copper or copper alloy, and water and has a pH of about 6 to about 12 so as to form an oxidized etch controlling layer and to uniformly remove the copper or copper alloy; and then removing the oxidized etch controlling layer with a non-oxidizing composition. Copper and copper alloy structure, having smooth upper surfaces are also provided.Type: GrantFiled: September 17, 2003Date of Patent: June 6, 2006Assignee: International Business Machines CorporationInventors: Emanuel Cooper, Bruce Furman, David Rath
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Publication number: 20060089000Abstract: In the back end of integrated circuits employing low-k interlevel dielectrics, etched structures are filled with a planarizing material comprising a cyclic olefin polymer and solvent; the next pattern to be etched is defined in a photosensitive layer above the planarizing layer; the pattern is etched in the dielectric and the planarizing material is stripped in a wet process that does not damage the interlevel dielectric.Type: ApplicationFiled: October 26, 2004Publication date: April 27, 2006Applicant: International Business Machines CorporationInventors: Ronald Della Guardia, Ranee Kwong, Wenjie Li, Qinghuang Lin, Dirk Pfeiffer, David Rath
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Publication number: 20060053491Abstract: The invention provides an improved network and methods of operation thereof for use in or with process control systems, computer-based manufacturing or production control systems, environmental control systems, industrial control system, and the like (collectively, “control systems”). Those networks utilize a unique combination of firewalls, intrusion detection systems, intrusion protection devices and/or other devices for hardening (e.g., security against hacking, intrusion or other mischievous conduct) and/or intrusion detection. The networks and methods have application, by way of example, in plants, sites and other facilities in which networks that support control systems interface with corporate, business or other networks.Type: ApplicationFiled: March 11, 2005Publication date: March 9, 2006Applicant: INVENSYS SYSTEMS, INC.Inventors: Bharat Khuti, Clayton Coleman, David Rath, Ernest Rakaczky, Jim Leslie, Juan Peralta, George Simpson
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Publication number: 20060043590Abstract: A chemical mechanical polishing (CMP) step is used to remove excess conductive material (e.g., Cu) overlying a low-k or ultralow-k interlevel dielectric layer (ILD) layer having trenches filled with conductive material, for a damascene interconnect structure. A reactive ion etch (RIE) or a Gas Cluster Ion Beam (GCIB) process is used to remove a portion of a liner which is atop a hard mask. A wet etch step is used to remove an oxide portion of the hard mask overlying the ILD, followed by a final touch-up Cu CMP (CMP) step which chops the protruding Cu patterns off and lands on the SiCOH hard mask. In this manner, processes used to remove excess conductive material substantially do not affect the portion of the hard mask overlying the interlevel dielectric layer.Type: ApplicationFiled: August 27, 2004Publication date: March 2, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven Shyng-Tsong Chen, Kaushik Kumar, Stephen Greco, Shom Ponoth, Terry Spooner, David Rath, Wei-Tsu Tseng
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Publication number: 20050158985Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.Type: ApplicationFiled: February 16, 2005Publication date: July 21, 2005Inventors: Shyng-Tsong Chen, Timothy Dalton, Kenneth Davis, Chao-Kun Hu, Fen Jamin, Steffen Kaldor, Mahadevaiyer Krishnan, Kaushik Kumar, Michael Lofaro, Sandra Malhotra, Chandrasekhar Narayan, David Rath, Judith Rubino, Katherine Saenger, Andrew Simon, Sean Smith, Wei-tsu Tseng
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Publication number: 20050081884Abstract: The present invention provides a method cleaning of semiconductor devices through heterogeneous nucleation of cavitation bubbles. Heterogeneous nucleation is performed by applying sonic energy to a cleaning solution and a phase material in order to remove unwanted particles from semiconductor devices. A surfactant may be added to the phase material and the cleaning solution.Type: ApplicationFiled: October 15, 2003Publication date: April 21, 2005Applicants: Infineon Technologies North America Corp., International Business Machines CorporationInventors: Ravikumar Ramachandran, David Rath
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Publication number: 20050056616Abstract: Copper and copper alloys are etched to provide uniform and smooth surface by employing an aqueous composition that comprises an oxidant, a mixture of at least one weak complexant and at least one strong complexant for the copper or copper alloy, and water and has a pH of about 6 to about 12 so as to form an oxidized etch controlling layer and to uniformly remove the copper or copper alloy; and then removing the oxidized etch controlling layer with a non-oxidizing composition. Copper and copper alloy structure, having smooth upper surfaces are also provided.Type: ApplicationFiled: September 17, 2003Publication date: March 17, 2005Applicant: International Business Machines CorporationInventors: Emanuel Cooper, Bruce Furman, David Rath
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Patent number: 6295998Abstract: A system is provided to prepare deionized water having a 100% saturated concentration of a gas, e.g., nitrogen, at a hot temperature, e.g., 50-85° C., and an attendant pressure, e.g., atmospheric pressure, to clean a semiconductor wafer, e.g., of silicon. The gas concentration of a first deionized water portion having a predetermined concentration of the gas at a cold temperature, e.g., 20-30° C., is adjusted in a gassifier chamber having a pressure pump and a pressure sensor, to provide a predetermined under-saturated concentration of the gas at the cold temperature. The temperature of the adjusted gas concentration first water portion is then adjusted by mixing therewith a second deionized water portion having a predetermined concentration of the gas at a predetermined very hot temperature, e.g., 80° C., in a predetermined ratio in a mixer having a temperature sensor.Type: GrantFiled: May 25, 1999Date of Patent: October 2, 2001Assignees: Infineon Technologies North America Corp., International Business Machines CorporationInventors: Stephan Kudelka, David Rath
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Patent number: 6167891Abstract: A system is provided to prepare deionized water having a 100% saturated concentration of a gas, e.g., nitrogen, at a hot temperature, e.g., 50-85° C., and an attendant pressure, e.g., atmospheric pressure, to clean a semiconductor wafer, e.g., of silicon. The gas concentration of deionized water having a predetermined concentration of the gas at a cold temperature, e.g., 15-30° C., is adjusted in a degassifier chamber having a vacuum pump and a pressure sensor, to provide an under-saturated concentration of the gas at the cold temperature corresponding to the saturated concentration thereof at the hot temperature and attendant pressure. The adjusted gas concentration water is then heated in a heating vessel having a heater and a temperature sensor, to the hot temperature to form a hot bath having such saturated gas concentration to clean the wafer, e.g., in a cleaning tank under megasonic vibrations.Type: GrantFiled: May 25, 1999Date of Patent: January 2, 2001Assignee: Infineon Technologies North America Corp.Inventors: Stephan Kudelka, David Rath