Abstract: A memory device includes an on-board cache system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The cache system operates in a manner that can be transparent to a memory controller to which the memory device is connected. Alternatively, the memory controller can control the operation of the cache system.

Abstract: A method, system, and article are provided for efficiently and effectively searching an electronic document collection. Each of the documents in the collection is pre-divided into sub-sections. One or more profiles are created, with each profile including a selection of one or more of the sections of the documents in the collection. In addition, a weight is assigned to each of the selected sections in the profile. Based upon the parameters of a query and selection of a profile, select sub-sections of each document are employed in a comparison of query data to the underlying document collection. A compilation of documents is created based upon all documents with data matching the query data within the sections of the document as identified in the submitted profile.

Abstract: A method, system, and article are provided for efficiently and effectively searching an electronic document collection. Each of the documents in the collection is pre-divided into sub-sections, and a static document vector is created for one or a combination of each sub-section of each document. A dynamic document vector is created for a query string submitted to the document collection. Based upon the parameters of the query, select sub-sections of each document are employed in a comparison of the dynamic document vector with select static document vectors. A compilation of IP documents is created based upon all associated select static document vectors that fall within a range of the dynamic document vector.

Abstract: A memory device includes an on-board cache system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The cache system operates in a manner that can be transparent to a memory controller to which the memory device is connected. Alternatively, the memory controller can control the operation of the cache system.

Abstract: A memory device includes an address protection system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The protection system is used to prevent at least some of a plurality of processors in a system from accessing addresses designated by one of the processors as a protected memory address. Until the processor releases the protection, only the designating processor can access the memory device at the protected address. If the memory device contains a cache memory, the protection system can alternatively or additionally be used to protect cache memory addresses.

Abstract: A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function.

Abstract: A memory device includes an on-board cache system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The cache system operates in a manner that can be transparent to a memory controller to which the memory device is connected. Alternatively, the memory controller can control the operation of the cache system.

Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

Abstract: An integrated circuit apparatus includes main logic for performing digital logic operations. The main logic is further comprised of a plurality of logic modules, each having at least one logic block associated with the logic module. Many times several logic blocks are associated with the logic modules. The main logic further also includes a number of input pins for receiving data and a number of output pins for outputting data from the main logic. Also included on the integrated circuit apparatus is testing logic for performing dynamic tests of the main logic. The testing logic further includes a first type of built-in testing logic for testing a first number of the logic modules of the main logic and a second type of built-in test logic for testing a second number of logic blocks. The second number of logic blocks connected to the second type of built-in scan logic are generally untestable using the first type of built-in logic.

Abstract: An apparatus and a method for extended-precision vector arithmetic capable of extremely long precision (i.e., precision to as many bits as a user desires or is limited to due to memory, disk-storage, or other resource constraints). Vector carry-out bits can be used as vector carry-in bits for successive operations. In performing add or subtract operations on integers that are longer than the word size of the computer, the operands a broken into word-sized parts which are used as operands. A vector of long-integer numbers is thus broken into a series of sub-vectors, each having word-sized elements. Vector add or subtract operations are performed successively on the sub-vectors, starting with the lowest-order sub-vectors. Carry-out (or borrow-out) bits from a first vector operation are used as carry-in (or borrow-in) bits for a successive vector operation.

Abstract: Payments in cash are submitted to a merchant at a point of sale. The payment transaction is effected electronically to credit the end user's intermediary account. Subsequent electronic communications between the intermediary account and a vendor site effect payment to the vendor for goods or services on behalf of the end user. This system leverages the existing credit card payment system in reverse so as to provide the convenience of submitting cash payments at a multitude of merchant locations.

Abstract: Payments in cash are submitted to a merchant at a point of sale. The payment transaction is effected electronically to credit the end user's intermediary account. Subsequent electronic communications between the intermediary account and a vendor site effect payment to the vendor for goods or services on behalf of the end user. This system leverages the existing credit card payment system in reverse so as to provide the convenience of submitting cash payments at a multitude of merchant locations.