Patents by Inventor David Richard Barach

David Richard Barach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230370382
    Abstract: In one embodiment, an offload platform is an compute platform, adjunct to a router or other packet switching device, that performs packet processing operations including determining an egress forwarding value corresponding to the next-hop node of the packet switching device to which to send an offload-platform processed packet. The offload platform downloads forwarding information from the router, and augments it, such as, but not limited to, representing interfaces of the router as identifiable virtual interface(s) on the offload platform, and including each of one or more next-hop nodes of the router represented as an identifiable virtual adjacency and identifiable tunnel (e.g., identified by the egress forwarding value). In one embodiment, the egress forwarding value is an Multiprotocol Label Switching (MPLS) label or Segment Routing Identifier. The router identifies packets of certain packet flows to send to the adjunct offload platform, rather than processing per its routing information base.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Ijsbrand Wijnands, Neale David Raymond Ranns, David Delano Ward, David Richard Barach
  • Publication number: 20230246967
    Abstract: In one embodiment, an offload platform is an compute platform, adjunct to a router or other packet switching device, that performs packet processing operations including determining an egress forwarding value corresponding to the next-hop node of the packet switching device to which to send an offload-platform processed packet. The offload platform downloads forwarding information from the router, and augments it, such as, but not limited to, representing interfaces of the router as identifiable virtual interface(s) on the offload platform, and including each of one or more next-hop nodes of the router represented as an identifiable virtual adjacency and identifiable tunnel (e.g., identified by the egress forwarding value). In one embodiment, the egress forwarding value is an Multiprotocol Label Switching (MPLS) label or Segment Routing Identifier. The router identifies packets of certain packet flows to send to the adjunct offload platform, rather than processing per its routing information base.
    Type: Application
    Filed: April 7, 2023
    Publication date: August 3, 2023
    Inventors: Ijsbrand Wijnands, Neale David Raymond Ranns, David Delano Ward, David Richard Barach
  • Patent number: 11627086
    Abstract: In one embodiment, an offload platform is an compute platform, adjunct to a router or other packet switching device, that performs packet processing operations including determining an egress forwarding value corresponding to the next-hop node of the packet switching device to which to send an offload-platform processed packet. The offload platform downloads forwarding information from the router, and augments it, such as, but not limited to, representing interfaces of the router as identifiable virtual interface(s) on the offload platform, and including each of one or more next-hop nodes of the router represented as an identifiable virtual adjacency and identifiable tunnel (e.g., identified by the egress forwarding value). In one embodiment, the egress forwarding value is an Multiprotocol Label Switching (MPLS) label or Segment Routing Identifier. The router identifies packets of certain packet flows to send to the adjunct offload platform, rather than processing per its routing information base.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: April 11, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Ijsbrand Wijnands, Neale David Raymond Ranns, David Delano Ward, David Richard Barach
  • Publication number: 20220368636
    Abstract: In one embodiment, an offload platform is an compute platform, adjunct to a router or other packet switching device, that performs packet processing operations including determining an egress forwarding value corresponding to the next-hop node of the packet switching device to which to send an offload-platform processed packet. The offload platform downloads forwarding information from the router, and augments it, such as, but not limited to, representing interfaces of the router as identifiable virtual interface(s) on the offload platform, and including each of one or more next-hop nodes of the router represented as an identifiable virtual adjacency and identifiable tunnel (e.g., identified by the egress forwarding value). In one embodiment, the egress forwarding value is an Multiprotocol Label Switching (MPLS) label or Segment Routing Identifier. The router identifies packets of certain packet flows to send to the adjunct offload platform, rather than processing per its routing information base.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 17, 2022
    Inventors: Ijsbrand Wijnands, Neale David Raymond Ranns, David Delano Ward, David Richard Barach
  • Patent number: 11398983
    Abstract: In one embodiment, an offload platform is an compute platform, adjunct to a router or other packet switching device, that performs packet processing operations including determining an egress forwarding value corresponding to the next-hop node of the packet switching device to which to send an offload-platform processed packet. The offload platform downloads forwarding information from the router, and augments it, such as, but not limited to, representing interfaces of the router as identifiable virtual interface(s) on the offload platform, and including each of one or more next-hop nodes of the router represented as an identifiable virtual adjacency and identifiable tunnel (e.g., identified by the egress forwarding value). In one embodiment, the egress forwarding value is an Multiprotocol Label Switching (MPLS) label or Segment Routing Identifier. The router identifies packets of certain packet flows to send to the adjunct offload platform, rather than processing per its routing information base.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: July 26, 2022
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Ijsbrand Wijnands, Neale David Raymond Ranns, David Delano Ward, David Richard Barach
  • Patent number: 10715439
    Abstract: One embodiment performs longest prefix matching operations in one or more different manners that provides packet processing and/or memory efficiencies in the processing of packets. In one embodiment, a packet switching device determines a set of one or more mask lengths of a particular conforming entry of a multibit trie or other data structure that matches a particular address of a packet via a lookup operation in a mask length data structure. A conforming entry refers to an entry which has less than or equal to a maximum number of different prefix lengths, with this maximum number corresponding to the maximum number of prefix lengths which can be searched in parallel in the address space for a longest matching prefix by the implementing hardware. The packet switching device then performs corresponding hash table lookup operation(s) in parallel in determining an overall longest matching prefix for the particular address.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: July 14, 2020
    Assignee: Cisco Technology, Inc.
    Inventors: Naader Hasani, Shishir Gupta, David Delano Ward, Mohammed Ismael Tatar, Shahin Habibi, Sreedhar Ravipalli, David Richard Barach
  • Publication number: 20200142752
    Abstract: A baseboard management controller (BMC) can physically partition the computing resources of a physical host into different resource groups for concurrently running a different operating system per resource group. The BMC can allocate a first processor of the host to a first resource group and a second processor of the host to a second resource group. The BMC can separate the memory of the host into a first memory range for the first processor and a second memory range for the second processor, and the BMC can limit access to the first memory range to the first processor and limit access to the second memory range to the second processor. The BMC can also distribute physical or virtual peripheral devices of the host between the first processor and the second processor.
    Type: Application
    Filed: December 30, 2019
    Publication date: May 7, 2020
    Inventors: Sape Mullender, David Richard Barach, Jim McKie, Peter Bosch
  • Publication number: 20200145335
    Abstract: In one embodiment, an offload platform is an compute platform, adjunct to a router or other packet switching device, that performs packet processing operations including determining an egress forwarding value corresponding to the next-hop node of the packet switching device to which to send an offload-platform processed packet. The offload platform downloads forwarding information from the router, and augments it, such as, but not limited to, representing interfaces of the router as identifiable virtual interface(s) on the offload platform, and including each of one or more next-hop nodes of the router represented as an identifiable virtual adjacency and identifiable tunnel (e.g., identified by the egress forwarding value). In one embodiment, the egress forwarding value is an Multiprotocol Label Switching (MPLS) label or Segment Routing Identifier. The router identifies packets of certain packet flows to send to the adjunct offload platform, rather than processing per its routing information base.
    Type: Application
    Filed: July 31, 2019
    Publication date: May 7, 2020
    Applicant: Cisco Technology, Inc., a California corporation
    Inventors: Ijsbrand WIJNANDS, Neale David Raymond RANNS, David Delano WARD, David Richard BARACH
  • Patent number: 10521273
    Abstract: A baseboard management controller (BMC) can physically partition the computing resources of a physical host into different resource groups for concurrently running a different operating system per resource group. The BMC can allocate a first processor of the host to a first resource group and a second processor of the host to a second resource group. The BMC can separate the memory of the host into a first memory range for the first processor and a second memory range for the second processor, and the BMC can limit access to the first memory range to the first processor and limit access to the second memory range to the second processor. The BMC can also distribute physical or virtual peripheral devices of the host between the first processor and the second processor.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: December 31, 2019
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Sape Mullender, David Richard Barach, Jim McKie, Peter Bosch
  • Publication number: 20190372896
    Abstract: One embodiment performs longest prefix matching operations in one or more different manners that provides packet processing and/or memory efficiencies in the processing of packets. In one embodiment, a packet switching device determines a set of one or more mask lengths of a particular conforming entry of a multibit trie or other data structure that matches a particular address of a packet via a lookup operation in a mask length data structure. A conforming entry refers to an entry which has less than or equal to a maximum number of different prefix lengths, with this maximum number corresponding to the maximum number of prefix lengths which can be searched in parallel in the address space for a longest matching prefix by the implementing hardware. The packet switching device then performs corresponding hash table lookup operation(s) in parallel in determining an overall longest matching prefix for the particular address.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 5, 2019
    Applicant: Cisco Technology, Inc.
    Inventors: Naader Hasani, Shishir Gupta, David Delano Ward, Mohammed Ismael Tatar, Shahin Habibi, Sreedhar Ravipalli, David Richard Barach
  • Patent number: 10397115
    Abstract: One embodiment performs longest prefix matching operations in one or more different manners that provides packet processing and/or memory efficiencies in the processing of packets. In one embodiment, a packet switching device determines a set of one or more mask lengths of a particular conforming entry of a multibit trie or other data structure that matches a particular address of a packet via a lookup operation in a mask length data structure. A conforming entry refers to an entry which has less than or equal to a maximum number of different prefix lengths, with this maximum number corresponding to the maximum number of prefix lengths which can be searched in parallel in the address space for a longest matching prefix by the implementing hardware. The packet switching device then performs corresponding hash table lookup operation(s) in parallel in determining an overall longest matching prefix for the particular address.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: August 27, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Naader Hasani, Shishir Gupta, David Delano Ward, Mohammed Ismael Tatar, Shahin Habibi, Sreedhar Ravipalli, David Richard Barach
  • Publication number: 20180357108
    Abstract: A baseboard management controller (BMC) can physically partition the computing resources of a physical host into different resource groups for concurrently running a different operating system per resource group. The BMC can allocate a first processor of the host to a first resource group and a second processor of the host to a second resource group. The BMC can separate the memory of the host into a first memory range for the first processor and a second memory range for the second processor, and the BMC can limit access to the first memory range to the first processor and limit access to the second memory range to the second processor. The BMC can also distribute physical or virtual peripheral devices of the host between the first processor and the second processor.
    Type: Application
    Filed: June 8, 2017
    Publication date: December 13, 2018
    Inventors: Sape Mullender, David Richard Barach, Jim McKie, Peter Bosch
  • Patent number: 9509614
    Abstract: An example method for load balancing in a network environment is provided and includes receiving a packet from a first stage load-balancer in a network environment, where the packet is forwarded from the first stage load-balancer to one of a plurality of second stage load-balancers in the network according to a hash based forwarding scheme, and routing the packet from the second stage load-balancer to one of a plurality of servers in the network according to a per-session routing scheme. The per-session routing scheme includes retrieving a session routing state from a distributed hash table in the network. In a specific embodiment, the hash based forwarding scheme includes equal cost multi path routing. The session routing state can include an association between a next hop for the packet and the packet's 5-tuple representing a session to which the packet belongs.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: November 29, 2016
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Hendrikus G. P. Bosch, David Richard Barach, Michael E. Lipman, Alessandro Duminuco, James N. Guichard, Humberto J. La Roche
  • Publication number: 20140379938
    Abstract: An example method for load balancing in a network environment is provided and includes receiving a packet from a first stage load-balancer in a network environment, where the packet is forwarded from the first stage load-balancer to one of a plurality of second stage load-balancers in the network according to a hash based forwarding scheme, and routing the packet from the second stage load-balancer to one of a plurality of servers in the network according to a per-session routing scheme. The per-session routing scheme includes retrieving a session routing state from a distributed hash table in the network. In a specific embodiment, the hash based forwarding scheme includes equal cost multi path routing. The session routing state can include an association between a next hop for the packet and the packet's 5-tuple representing a session to which the packet belongs.
    Type: Application
    Filed: June 20, 2013
    Publication date: December 25, 2014
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Hendrikus G. P. Bosch, David Richard Barach, Michael E. Lipman, Alessandro Duminuco, James N. Guichard, Humberto J. La Roche
  • Patent number: 8005098
    Abstract: Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with load balancing across multiple network address translation (NAT) instances and/or processors. N network address translation (NAT) processors and/or instances are each assigned a portion of the source address traffic in order to load balance the network address translation among them. Additionally, the address space of translated addresses is partitioned and uniquely assigned to the NAT processors and/or instances such that the identification of the assigned NAT processor and/or instance associated with a received translated address can be readily determined there from, and then used to network address translate that received packet.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: August 23, 2011
    Assignee: Cisco Technology, Inc.
    Inventors: David Richard Barach, Cullen Jennings, David Delano Ward
  • Patent number: 7961636
    Abstract: An intermediate network node is configured to forward a plurality of packets concurrently, e.g., as a vector, rather than one packet at a time. As such, the node can load a single sequence of forwarding instructions that may be repeatedly executed for packets in the vector. In addition, the intermediate network node adaptively controls the rate at which it processes data packets through a directed forwarding graph. To that end, the intermediate node is configured to dynamically select the number of packets per vector, i.e., vector size, processed at each node of the forwarding graph. Further, the intermediate node also may be configured to dynamically select timing intervals for one or more “node timers” used to control the rate at which packets traverse through the graph. Illustratively, the vector size and node-timer intervals are selected so that the average latency through the forwarding graph is less than a predetermined target latency, e.g., 50 microseconds (?s).
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: June 14, 2011
    Assignee: Cisco Technology, Inc.
    Inventors: David Richard Barach, Eliot Dresselhaus
  • Publication number: 20100061380
    Abstract: Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with load balancing across multiple network address translation (NAT) instances and/or processors. N network address translation (NAT) processors and/or instances are each assigned a portion of the source address traffic in order to load balance the network address translation among them. Additionally, the address space of translated addresses is partitioned and uniquely assigned to the NAT processors and/or instances such that the identification of the assigned NAT processor and/or instance associated with a received translated address can be readily determined there from, and then used to network address translate that received packet.
    Type: Application
    Filed: September 5, 2008
    Publication date: March 11, 2010
    Applicant: Cisco Technology, Inc., a corporation of California
    Inventors: David Richard Barach, Cullen Jennings, David Delano Ward
  • Patent number: 7325059
    Abstract: The present invention provides a technique for efficiently looking up address-routing information in an intermediate network node, such as a router. To that end, the node locates routing information stored in its memory using one or more “lookup” tables (LUT) which can be searched using a small, bounded number of dependent lookups, thereby reducing the number of dependent lookups conventionally performed. The LUTs are arranged so each table provides routing information for network addresses whose subnet mask lengths are within a different range (“stride”) of mask lengths. According to the technique, the node locates a network address's routing information by searching the LUTs, in order of decreasing prefix lengths, until the routing information is found. Preferably, several tables are searched in parallel. A match in a LUT may further point to a small MTRIE that enables the final bits of a prefix to be matched. That final MTRIE is searched using a relatively small, bounded number of dependent lookups.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: January 29, 2008
    Assignee: Cisco Technology, Inc.
    Inventors: David Richard Barach, Bobby Batacharia
  • Patent number: 7289441
    Abstract: An intermediate network node is configured to drop or reject new client sessions when its available resources are below a predetermined level. In this manner, the intermediate node can efficiently process a large number of new session attempts at substantially the same time. The intermediate node monitors the availability of its resources by calculating a load metric. The load metric is based on one or more partial load metrics, each corresponding to a different system resource. The load metric is compared with a predetermined value to determine whether the node has enough available resources to continue establishing new client sessions. Alternatively, the intermediate node rejects new client sessions when a total number of allocated “abstract resource units” rises above a predetermined level. That is, client sessions are assigned a predetermined number of abstract resource units on a per-protocol basis and a resource counter stores the number of abstract resource units allocated by the intermediate node.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: October 30, 2007
    Assignee: Cisco Technology, Inc.
    Inventor: David Richard Barach
  • Patent number: 7117308
    Abstract: A data path protocol eliminates most of the conventional read transactions required to transfer data between devices interconnected by a split transaction bus, such as a HyperTransport (HPT) bus. To that end, each device is configured to manage its own set of buffer descriptors, unlike previous data path protocols in which only one device managed all the buffer descriptors. As such, neither device has to perform a read transaction to retrieve a “free” buffer descriptor from the other device. As a result, only write transactions are performed for transferring descriptors across the HPT bus, thereby decreasing the amount of traffic over the bus and eliminating conventional latencies associated with read transactions. In addition, because descriptors are separately managed in each device, the data path protocol also conserves processing bandwidth that is traditionally consumed by managing ownership of the buffer descriptors within a single device.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: October 3, 2006
    Assignee: Cisco Technology, Inc.
    Inventors: John W. Mitten, Christopher G. Riedle, David Richard Barach, Kenneth H. Potter, Jr., Kent Hoult, Jeffery B. Scott