Abstract: A computer system in which a graphics accelerator unit manages page faulting of texture data invisibly to the host processor.

Abstract: A geometry and lighting graphics accelerator with an improved clipping process. Clipping is performed prior to any calculation or evaluation of primitives for lighting, texture, fog, or color. Barycentric coordinates are used to define all vertices: original, intermediate, and final intersection points. Use of barycentric coordinates results in less storage space. A circular buffer is used during the clipping process to store input and output polygons. Use of the circular buffer also results is reduced storage requirements.

Abstract: A graphics system architecture, in which condensed cache tags for texture are achieved by a remapping operation which exploits the relation between the level-of-detail parameter of mip mapping and the maximum resolution.

Abstract: A texture caching controller, located on the graphics card, handles address logical-to-physical translation for texture addresses which are not downloaded to level-1 memory due to low use or dynamically changing values. This offloads texture memory management duties from the host.

Abstract: A system and method for increasing rendering efficiency in pipelined graphics systems. In the disclosed embodiments, reads of pixel information during the rendering of a primitive are suspend if the pixel information has not been updated by a previous primitive. In some embodiments, reads of pixel information are also suspended periodically when a table tracking the information becomes full. In some embodiments a Read Monitor Unit 108 controlled by the graphics system's Memory Controller 106 is used to track pixels which have been affected by rendered primitives. In some embodiments, a history list is used to avoid suspension of reads for antialiased lines. In a particular embodiment, the table used to track affected pixels is two-bits, the first bit tracking whether the pixel has been touched by a primitive since the last SuspendReads command was invoked and the second bit tracking whether the pixel has been touched by the current primitive. Both bits are reset when a power on or SuspendReads command occurs.

Abstract: Patch-parallelized plane equation evaluation, for triangle membership testing, is performed with reduced dynamic range by referencing x and y coordinates to a base location which is (for each patch) in or near the patch.

Abstract: A graphics memory architecture in which row addresses are permuted, in a basically tile-oriented storage architecture, so that fast parallel access is provided both by scanlines (for video operations) and also by tiles (for graphics operations).

Abstract: An antialiased mask generation technique where a patch of pixels is tested in parallel for fragment membership, and this test is looped with successive subpixel vector offsets from a programmed set. Antialiasing smoothness can be traded off for throughput by varying the size of the programmed set.

Abstract: A tile-oriented graphics processing system in which an additional level of caching is provided locally, at the output of a patch-processing graphics computation block. This additional local storage buffers the current tile, so that repeated accesses to the same tile can avoid pipelining delays connected with access to the main cache. (Even an on-chip cache, in a large chip, can impose access delays which are significant in relation to the computation speeds involved.

Abstract: A 3D graphics accelerator in which vertex data is locally cached, at individual rendering subsystems, in circular buffers which are NOT large enough to hold the maximum number of data fields for the maximum number of vertices which can be parallel-processed. Instead, the circular buffers are preferably made large enough to hold the maximum number of data fields for a minimum useful number of vertices; the same buffers can also be used to hold a smaller number of data fields for the maximum number of vertices.

Abstract: A graphics accelerator architecture in which instructing on a data stream which includes a mixture of scalars and short vectors (i.e. 2-, 3- or 4-vectors) are defined with an argument in the opcode which specifies the data type(s) being manipulated. The sequencer expands each of these opcodes on the fly to produce an appropriate series of instructions for the scalar processor to execute. This is particularly advantageous with the limited set of vector lengths handled in rendering operations.

Abstract: A graphics processing unit which both pre-fetches and preloads texture data. Preferably a cache line is preassigned to the texture data approximately as soon as a miss occurs.

Abstract: A 3D graphics processing unit which performs rapid context switching from normal rendering tasks to isochronous tasks when required. Preferably a secondary rasterizer, having less capability than the primary rasterizer, is provided in hardware, so that the primary rasterizer does not have to be context-switched when isochronous tasks are started.

Abstract: A specialized processing chip (e.g. a graphics accelerator) in which the host interface provides access to the diagnostic registers in most of the complex logic on the chip, except for the host interface itself. This advantageously permits the host CPU to obtain direct access to register contents in the specialized chip.

Abstract: A graphics system in which the dedicated graphics memory is doubly virtualized: it can be paged into host physical memory, and also, beyond that, into host bulk storage. Portions of host physical memory which are needed to support the graphics memory management process can be locked down.

Abstract: A computer system which includes at least one host CPU; at least two separate rasterizer units, interconnected to process at least some graphics rendering tasks jointly; and a shared graphics memory manager which sends requested data to both said rasterizers simultaneously.

Abstract: A graphics accelerator which includes a dedicated virtual memory manager which manages at least some host memory, as well as dedicated graphics memory, and which manages memory during mipmapping using at least two separate pools of memory.

Abstract: A 3D graphics processing unit which performs rapid context switching from normal rendering tasks to isochronous tasks when required. Preferably a secondary rasterizer, having less capability than the primary rasterizer, is provided in hardware, so that the primary rasterizer does not have to be context-switched when isochronous tasks are started.

Abstract: A specialized processing chip (e.g. a graphics accelerator) in which the host interface provides access to the diagnostic registers in most of the complex logic on the chip, except for the host interface itself. This advantageously permits the host CPU to obtain direct access to register contents in the specialized chip.

Abstract: A graphics accelerator with a byte-tiled memory architecture, and a high-speed image download path which provides higher bandwidth than the message-passing pipeline.