Abstract: When two asynchronous signals may occur at approximately the same time, only one of the signals being able to control consequent events, a circuit accounts for the conflict situation by selectively adding a delay until the conflict situation has settled. While the circuit does not determine which asynchronous event may control, the selective delay extends the time for the decision to be made. This circuit provides high reliability while minimizing delays and eliminates the need for indiscriminately adding a delay to each asynchronous event so as to resolve conflict situations. The circuit has particular applicability to volatile memory systems wherein conflict between processor requests and refresh requests to memory occur and allows processor requests to proceed with minimum delay in nearly all situations.