Abstract: A test mode matrix circuit in an integrated circuit switches signal lines internal to the integrated circuit in a manner that allows an embedded microprocessor within the integrated circuit to be fully functionally tested using standard test vectors applied to the integrated circuit, and which allows for debugging the code written for an embedded microprocessor core by connecting an in-circuit emulator (ICE) to the integrated circuit. The test mode matrix circuit operates in a number of mutually exclusive modes, each of which is suitably selected via control signal inputs to the test mode matrix. The test mode matrix circuit couples signals from the embedded microprocessor to the application-specific logic without passing through off-chip drivers/receivers. Multiple microprocessors and corresponding test mode matrices may also be implemented on the same integrated circuit.

Abstract: A test mode matrix circuit in an integrated circuit switches signal lines internal to the integrated circuit in a manner that allows an embedded microprocessor within the integrated circuit to be fully functionally tested using standard test vectors applied to the integrated circuit, and which allows for debugging the code written for an embedded microprocessor core by connecting an in-circuit emulator (ICE) to the integrated circuit. The test mode matrix circuit operates in a number of mutually exclusive modes, each of which is suitably selected via control signal inputs to the test mode matrix. The test mode matrix circuit couples signals from the embedded microprocessor to the application-specific logic without passing through off-chip drivers/receivers. Multiple microprocessors and corresponding test mode matrices may also be implemented on the same integrated circuit.

Abstract: A Direct Memory Access (DMA) Acceleration Device for substantially increasing a data transfer rate between a system memory and an Input/Output (I/O) device for use in a data processing system. The DMA Acceleration Device enables the system to subtantially double a data transfer rate between the system memory and the I/O device by generating necessary control and address signals. In a receive operation, the DMA Acceleration Device reads the data from the I/O device while the host processor simultaneously writes the previous data to the system memory. Similarly, in a transmit operation, the DMA Acceleration Device writes the data to the I/O device while the host processor simultaneously reads the subsequent data from the system memory. Transmit and Receive State Machines of the DMA Acceleration Device are programmed to control the sequencing of signals during the DMA mode, while being absolutely transparent to the system in a non-DMA mode of operation.