Abstract: Bus communications are effected. In accordance with one or more example embodiments, a bus circuit is configured for communicating data in accordance with a main protocol (e.g., as a default), and for communicating with an alternate protocol when signals corresponding to the main protocol are not present. In some implementations, a sense circuit is used with input pins to sense a type of signal for bus communications, and to control communications on the bus with a protocol appropriate for the sensed signals, and for a main protocol when main protocol signals are sensed (e.g., for a default bus operation, or for test operation).

Abstract: Bus communications are effected. In accordance with one or more example embodiments, a bus circuit is configured for communicating data in accordance with a main protocol (e.g., as a default), and for communicating with an alternate protocol when signals corresponding to the main protocol are not present. In some implementations, a sense circuit is used with input pins to sense a type of signal for bus communications, and to control communications on the bus with a protocol appropriate for the sensed signals, and for a main protocol when main protocol signals are sensed (e.g., for a default bus operation, or for test operation).

Abstract: A computer system includes a host processor, a first PCI bus, a second PCI bus and a bus bridge. The first PCI bus is coupled with the host processor. The bus bridge interconnects the first and second PCI buses. The bus bridge includes a first portion having a first bridge memory, a second portion having a second bridge memory, and a latency inducing serial bus interconnecting the first portion and the second portion. A method is also taught.

Abstract: An apparatus is provided for interfacing a processor with a bus of a computer system wherein the processor performs burst read operations in both a sequential and a non-sequential manner and the bus is incapable of supporting burst operations that are non-sequential. The apparatus includes an interface adaptor circuit that is coupled between the processor and the bus. The interface adaptor circuit is operative as a burst order translator between the processor and the bus, and has a bridge configured to connect together the processor and the bus. The bridge is operative to translate processor burst operations into operations supported by the bus. The bridge has a processor interface coupled between the processor and the interface adaptor circuit and a bus interface coupled between the bus and the interface adaptor circuit.

Abstract: A computer system includes a host processor, a first PCI bus, a second PCI bus and a PCI-to-PCI bridge. The first PCI bus is coupled with the host processor. The PCI-to-PCI bridge interconnects the first and second PCI buses. The PCI-to-PCI bridge includes a first portion and a second portion. The first portion includes a first configuration register and the second portion includes a second configuration register. A method is also taught.

Abstract: A direct memory access engine (DMA) system and method for maximizing DMA transfers of arbitrarily aligned data. The present invention utilizes physical region descriptors (PRD) stored in memory to track locations and descriptions of scattered data in a main memory. The direct memory access circuit retrieves the data in accordance with the PRD and configures the data into pieces such that intermediate pieces of data between a first piece and a last piece are the maximum amount of information a communication burst is capable of transferring and the intermediate pieces of data are aligned to a natural boundary address. The DMA engine also communicates the first piece of data and the last piece of data in a manner that minimizes memory accesses and in transfer sizes that are compatible with requirements and limitations of a system in which DMA engine is implemented.

Abstract: A multiple processor circuit arrangement utilizes a master processor which controls the operational state of a slave processor by programming internal control registers on the slave processor. In addition, a stack-based processor utilizes a stack cache for accelerating stack access operations and thereby accelerating the overall performance of the processor. When the stack-based processor is utilized as a slave processor in the aforementioned master/slave multi-processor computer system the slave processor is optimized to process platform-independent program code such as Java bytecodes, thereby permitting fast and efficient execution of both program code native to the master processor as well as platform-independent program code that is in effect native to the slave processor.

Abstract: A multiple processor circuit arrangement utilizes a master processor which controls the operational state of a slave processor by programming internal control registers on the slave processor. In addition, a stack-based processor utilizes a stack cache for accelerating stack access operations and thereby accelerating the overall performance of the processor. When the stack-based processor is utilized as a slave processor in the aforementioned master/slave multi-processor computer system the slave processor is optimized to process platform-independent program code such as Java bytecodes, thereby permitting fast and efficient execution of both program code native to the master processor as well as platform-independent program code that is in effect native to the slave processor.

Abstract: A hot docking system and method for managing and detecting hot docking of bus cards. The hot docking system detects the load impedance at the power pins of the bus connector to determine whether a card has been inserted. When insertion is detected, bus activity on the connector is ceased until the card is completely inserted which is indicated by signals present on card detect pins which are mechanically shorter that the bus signal pins and thereby provide this insertion signal after all other connections are complete. The power supply pins are mechanically longer than the bus signal pins thereby providing an early indication that a card has been inserted. On removal of the card, the card detect pins disconnect before the bus signal pins or the power supply pins, signaling the system to halt bus activity but maintain power on the connector until the card is completely removed.

Abstract: The present invention, generally speaking, provides for pin sharing between two or more disparate memory devices, a dynamic memory device such as a CD ROM drive or the like and a static memory device such as a ROM integrated circuit. In accordance with one embodiment of the invention, a common set of pins of an integrated circuit are used to interface to a plurality of different information storage device including both a dynamic storage device and static storage device by, in a first mode, using a first subset of the common set of pins to carry data information for one of the devices and, in a second mode, using the first subset of pins to carry address information for another one of the devices. In accordance with another embodiment of the invention, an integrated circuit includes a set of I/O pins, a multiplexer coupled to the set of I/O pins, and multiple device controllers coupled to the multiplexer, including both a dynamic storage device controller and a static storage device controller.

Abstract: A multiple processor circuit arrangement utilizes a master processor which controls the operational state of a slave processor by programming internal control registers on the slave processor. In addition, a stack-based processor utilizes a stack cache for accelerating stack access operations and thereby accelerating the overall performance of the processor. When the stack-based processor is utilized as a slave processor in the aforementioned master/slave multi-processor computer system the slave processor is optimized to process platform-independent program code such as Java bytecodes, thereby permitting fast and efficient execution of both program code native to the master processor as well as platform-independent program code that is in effect native to the slave processor.

Abstract: A translating circuit coupled to a processor and memory of a computer system translates platform-independent instructions such as Java bytecodes into corresponding native instructions for execution by the processor. In one embodiment, the translating circuit is incorporated into the same integrated circuit device as the processor. In another embodiment, the translating circuit is provided within one or more external integrated circuit devices. One or more look-up tables map platform-independent instructions into one or more native instructions for the processor, thereby minimizing software-based interpretation of platform-independent program code. Moreover, platform-independent instructions are mapped to native instructions on-the-fly, or alternatively, in blocks prior to execution using a state machine.

Abstract: A universal disk controller for microprocessor systems is capable of use as a PCI interface with either SCSI drives or IDE drives. To effect selection of the appropriate one of the IDE or SCSI drives for use with the interface, a configuration logic circuit is coupled with a PCI bus master interface to select an IDE state machine or an SCSI state machine, both of which are coupled with a combined IDE/SCSI interface having common pins for connection to the appropriate IDE or SCSI drive for operation with the controller. Consequently, separate chips for providing interfaces between a PCI bus and either an IDE or an SCSI drive are not required. The system permits switching between IDE and SCSI drives according to the application with which it is being used.

Abstract: A keyboard controller supports both a first keyboard/mouse interface and a second keyboard/mouse interface. Data is routed between the first keyboard/mouse interface and a first host interface when the first host interface is active. Data is routed between the first keyboard/mouse interface and a first shell when a second host interface is active. The first shell provides compatible connection between the first keyboard/mouse interface and the second host interface. Data is routed between the second keyboard/mouse interface and the second host interface when the second host interface is active. Data is routed between the second keyboard/mouse interface and a second shell when the first host interface is active. The second shell provides compatible connection between the second keyboard/mouse interface and the first host interface.

Abstract: The present invention relates to a clock recovery system which allows for stable clock information to be extracted from a serial data stream with defined jitter characteristics. The clock recover circuit is comprised of a flip flop which is used for receiving the serial data stream and for outputting stable clock information. A sampling clock circuit is coupled to the flip flop for sending a signal which reflects a center area of each bit period in the serial data stream when a transition occurs in the serial data stream.

Abstract: A method for preventing deadlocks is used in a computing system in which a host bus is connected to a first input/output bus through a first bridge and the first input/output bus is connected to a second input bus through a second bridge. When transferring data from a first input/output device on the second input/output bus to a memory on the host bus, the first input/output device requests mastership of the second input/output bus. Before granting mastership to the first input/output device, the second bridge instructs the first bridge to flush and disable write buffers within the first bridge. After the write buffers have been flushed, the first input/output device is granted mastership of the second input/output bus. The second bridge requests mastership of the first input/output bus by asserting a request signal on a request line. The first bridge then obtains mastership of the host bus in order to allow the transfer of the data from the first input/output device to the memory.

Abstract: Power is conserved in a computing system by detecting when a user's hands are not placed over a keyboard for the computing system. When it is detected that the user's hand are not placed over the keyboard power to a display for the computing system is reduced. For example, the hands are detected by generating and detecting ultrasound waves. In one embodiment of the present invention, the ultrasound waves are generated and detected from positions on a case of the computing system so that when the user's hands are placed on the keyboard, the user's hands block a portion of the ultrasound waves from being detected. In another embodiment, the ultrasound waves are generated and detected from positions on a case of the computing system so that when the user's hands are placed on the keyboard, the user's hands reflect a portion of the ultrasound waves so that the portion of the ultrasound waves are detected.

Abstract: Signalling apparatus are used for monitoring a clock signal from a system controller to a processor. If the clock signal is low, indicating that the processor is disabled, the signalling apparatus will place the cache memory in a "sleep" mode. Thus, the signalling apparatus allow a computer system, upon which the signalling apparatus is a part of, to lower its power consumption. If the computer system is a portable computer system, the signalling apparatus will lower power consumption thereby extending the lifetime of the portable computer's batteries.

Abstract: A thermal management device for controlling the temperature of a computer processor chip, by controlling the operating speed of the processor, including a temperature sensitive circuitry incorporated within a packaged clock chip for connection to a processor. A thermal management method for controlling the temperature of a computer processor chip includes sensing a temperature with a temperature dependent circuitry integrally formed in a packaged clock chip, in which the sensed temperature is a function of the temperature of the computer processor chip, generating a clock control signal with the temperature dependent circuitry and sending the clock control signal to a clock generator also integrally formed in the clock chip, and sending a clock signal from the clock generator to the computer processor chip in order to control the operating frequency, and thus the temperature, of the processor.