Abstract: A memory module, a partial address generator, and a controllable pseudo-random number generator are provided to a digital video system for generating values used to perform static/dynamic companding for transfer functions shifting/modifying digital video data. The memory module is used for storing an integrated collection of lookup tables comprising lookup tables having values used to perform linear/non-linear static and dynamic companding. The values used to perform static/dynamic companding are retrieved using composite addresses. During each access, the higher order bits are generated by the partial address generator, and the lower order bits are set to equal the current digital video data value being shifted/modified. The partial address generator generates the higher order bits of the composite address based on a number of companding scheme selection control signals and a pseudo-random number received as inputs.

Abstract: Under one embodiment, a first and a second similarly constituted detector, and an OR gate coupled to the two detectors, are provided to a digital video system. The first detector detects quantization errors of numerically adjacent values in vertically adjacent pixels of a current frame. The second detector detects quantization errors of numerically adjacent values in horizontally adjacent pixels in the current frame. The OR gate is used to determine whether quantization errors of numerically adjacent values are detected in at least one of the two spatial dimensions of pixel adjacency in the current frame. In one variation of this embodiment, a potential quantization error lookup table that supports concurrent lookups for vertically and numerically adjacent quantization error detection as well as horizontally and numerically adjacent quantization error detection is used and shared between the two detectors.

Abstract: A flexible computer controlled non-linear transform generator is disclosed which employs a random access memory (RAM) lookup table (LUT) having programmable controlled address and data paths and an address multiplexer which is programmed to dynamically control LUT loading and live data transformation. A MASK register is programmed to dynamically modify the number of banks of memory in the LUT, an ADDRESS SELECT register is programmed to set the access mode of for the LUT--either random access mode, auto-increment mode, or live data mode, a BIT WIDTH register is programmed to set the width of the data stored in the LUT, and a BASE ADDRESS register is programmed with the starting address for loading the LUT in auto-increment mode. During live data transformation, a digitized input signal is used to address the LUT, while the contents of the LUT at the addressed location provides a digitized output signal according to a predefined transfer function.

Abstract: A hardware implementation of a digitized image corrector is disclosed that converts a colorimetric representation of an original image into a new representation based upon the colors of the original and target images, as well as user supplied artistic parameters. The digitized image corrector receives digitized Red, Green and Blue input signals that comprise a colorimetric representation of an original film scene, and generates digitized Red, Green, and Blue output signals according to the specifications of SMPTE 240 M. The digitized image corrector is comprised of four identical hardware correction modules, which are coupled to receive correction parameters from an external source. Each module has a bypass switch for entering a bypass mode, which is used for reconfiguration of the module's correction parameters without affecting the output image.

Abstract: A method and apparatus for quickly adding at least three multi-bit binary numbers. The addition is divided into two stages. In Stage I, each of the addends are grouped into like-ordered multi-bit clusters and the corresponding clusters of the addends are added together using Programmable Read Only Memory (PROM) integrated circuits (ICs) yielding several intermediate sums. In Stage II, the intermediate sums are combined to yield a final sum using Programmable Array Logic (PAL, PAL is a trademark of Monolithic Memories, Inc.) ICs. Furthermore, the final sum is rounded in Stage I (and clipped if necessary in a third stage) before being provided as output. Clipping is achieved by setting the output sum to zero if the final sum is negative and setting the output sum to a predetermined threshold value if the final sum exceeds the threshold value.