Abstract: An electronic device including a digital circuit to be compensated and a compensation device for compensating PVT variations of this digital circuit. This compensation device is arranged also for controlling the operating speed of the digital circuit and can also be arranged for equalising a rise time and a fall time of a logic gate including the transistors of the digital circuit. The electronic device implements a first loop, allowing to control the operating speed of the digital circuit by exploiting the same voltage at the compensation terminals of the compensation device and at the terminals at the digital circuit and at a critical path replica module allowing to control the threshold voltages of the respective transistors. The electronic device can implement also a second loop allowing to equalise the rise and fall times of a logic gate including the transistors of the digital circuit.

Abstract: A compensation device for compensating PVT variations of an analog and/or digital circuit. The compensation device includes a transistor having a first terminal, a second terminal, a third terminal, and a fourth terminal allowing to modify a threshold voltage of the transistor. The transistor is configured to be in saturation region. The voltage at the third terminal has a predetermined value and the difference between the voltage at the second terminal and the voltage at the third terminal has a predetermined value. A current generation module is configured to generate a current of a predetermined value. A compensation module is configured to force this current to flow between the first terminal and the third terminal by adjusting the voltage of the fourth terminal.

Abstract: An electronic device including a digital circuit to be compensated and a compensation device for compensating PVT variations of this digital circuit. This compensation device is arranged also for controlling the operating speed of the digital circuit and can also be arranged for equalising a rise time and a fall time of a logic gate including the transistors of the digital circuit. The electronic device implements a first loop, allowing to control the operating speed of the digital circuit by exploiting the same voltage at the compensation terminals of the compensation device and at the terminals at the digital circuit and at a critical path replica module allowing to control the threshold voltages of the respective transistors. The electronic device can implement also a second loop allowing to equalise the rise and fall times of a logic gate including the transistors of the digital circuit.

Abstract: A compensation device for compensating PVT variations of an analog and/or digital circuit. The compensation device includes a transistor having a first terminal, a second terminal, a third terminal, and a fourth terminal allowing to modify a threshold voltage of the transistor. The transistor is configured to be in saturation region. The voltage at the third terminal has a predetermined value and the difference between the voltage at the second terminal and the voltage at the third terminal has a predetermined value. A current generation module is configured to generate a current of a predetermined value. A compensation module is configured to force this current to flow between the first terminal and the third terminal by adjusting the voltage of the fourth terminal.

Abstract: A wristwatch, which comprises an atomic oscillator comprising a system for detecting the beat frequencies obtained by the Raman effect.

Abstract: The temperature compensated timing signal generator comprises a crystal oscillator that generates a reference time signal, and a divider circuit that receives the reference time signal as input and outputs a coarse time unit signal, the coarse time unit signal having an actual frequency deviating from a desired frequency as a function of temperature of the crystal oscillator. The signal generator also includes a high frequency oscillator configured to generate an interpolation signal having a frequency greater than the frequency of the crystal oscillator. A finite state machine computes a deviation compensating signal as a function of temperature, the signal comprises an integer part representative of an integer number of pulses to be inhibited or injected in the divider circuit and a fractional part representative of how much the output of a new time unit signal pulse should further be delayed to compensate for any remaining deviation.

Abstract: The temperature compensated timing signal generator comprises a crystal oscillator that generates a reference time signal, and a divider circuit that receives the reference time signal as input and outputs a coarse time unit signal, the coarse time unit signal having an actual frequency deviating from a desired frequency as a function of temperature of the crystal oscillator. The signal generator also includes a high frequency oscillator that generates an interpolation signal having a frequency greater than the frequency of the crystal oscillator. A finite state machine computes a deviation compensating signal as a function of the temperature signal, the signal comprises an integer part representative of an integer number of pulses to be inhibited or injected in the divider circuit and a fractional part representative of how much the output of a new time unit signal pulse should further be delayed to compensate for any remaining deviation.

Abstract: A frequency synthesizer includes: a first oscillator (1) controlled by a first control device, the first oscillator having a high quality factor that is greater than 300 and produces a first clock signal (2) RF having a fixed frequency, the first control device (30) controlling the frequency of the first controlled oscillator (1) on the basis of a first reference frequency; a second oscillator (3) controlled by a second control device and producing a second clock signal (4); the second control device (31) controlling the frequency of the second controlled oscillator (3) on the basis of a second reference frequency; and an integer frequency divider (5) dividing the frequency of the second clock signal (4) by a variable integer factor N1 and producing a third clock signal (6), the frequency of which is continuously variable by modifying the factor N1 and the control of the second oscillator.

Abstract: A wristwatch, which comprises an atomic oscillator comprising a system for detecting the beat frequencies obtained by the Raman effect.

Abstract: A device for compensating for the frequency of a resonator includes (a) a temperature sensor, (b) a sequencer determining a second compensation signal on the basis of the temperature and corresponding to a positive value N, and a third compensation signal on the basis of the temperature corresponding to a ratio between a positive integer S and N, S being lower than or equal to N, and (c) a variable counter receiving the compensation signals and generating a fourth output signal every N periods of a clock signal from the resonator and generating a fifth signal for modifying the charge capacity of the resonator.

Abstract: A frequency synthesizer includes: a first oscillator (1) controlled by a first control device, the first oscillator having a high quality factor that is greater than 300 and produces a first clock signal (2) RF having a fixed frequency, the first control device (30) controlling the frequency of the first controlled oscillator (1) on the basis of a first reference frequency; a second oscillator (3) controlled by a second control device and producing a second clock signal (4); the second control device (31) controlling the frequency of the second controlled oscillator (3) on the basis of a second reference frequency; and an integer frequency divider (5) dividing the frequency of the second clock signal (4) by a variable integer factor N1 and producing a third clock signal (6), the frequency of which is continuously variable by modifying the factor N1 and the control of the second oscillator.

Abstract: The invention relates to a silicon resonator (10) of the tuning-fork type in which the linear frequency drift depending on the temperature is compensated. The resonator includes a silicon base (14), a plurality of parallel arms (11, 12, 13) capable of vibrating and actuator (18, 21, 22), wherein the arms include a silicon layer provided between two layers of silicon oxide having a thickness, relative to that of the silicon layer, such that it ensures the first-order compensation of the resonator thermal drift.

Abstract: A phase-locked loop includes: a variable oscillator connected to a first resonator, said oscillator being able to deliver an output signal at a first output frequency Fout1, a first frequency divider receiving the output signal and able to convert it into a divided frequency signal Fout1/n, a reference oscillator connected to a second so-called reference resonator, delivering a reference signal at a low reference frequency Fref, generating an electrical dissipation lower than a microampere, a phase comparator measuring the phase error between the divided frequency signal Fout1/n and the reference signal and being able to produce a test signal, a low-pass filter or an integrating circuit able to filter the test signal and able to generate a voltage or a control word designed to control the voltage-controlled or digitally controlled oscillator.

Abstract: A device for compensating for the frequency of a resonator, includes: a temperature sensor for the resonator; a sequencer determining a second compensation signal on the basis of the temperature value corresponding to a positive value N, and a third compensation signal on the basis of the temperature value, corresponding to a ratio between a positive integer S and N, S being lower than or equal to N; a variable counter receiving the compensation signals and generating a fourth output signal every N periods of a clock signal from the resonator and generating a fifth signal for modifying the charge capacity of the resonator.

Abstract: The invention relates to a silicon resonator (10) of the tuning-fork type in which the linear frequency drift depending on the temperature is compensated. The resonator includes a silicon base (14), a plurality of parallel arms (11, 12, 13) capable of vibrating and actuator (18, 21, 22), wherein the arms include a silicon layer provided between two layers of silicon oxide having a thickness, relative to that of the silicon layer, such that it ensures the first-order compensation of the resonator thermal drift.

Abstract: The present invention concerns a phase-locked loop comprising: a variable oscillator connected to a first resonator, said oscillator being able to deliver an output signal at a first output frequency Fout1, a first frequency divider receiving said output signal and able to convert it into a divided frequency signal Fout1/n, a reference oscillator connected to a second so-called reference resonator, delivering a reference signal at a low reference frequency Fref, generating an electrical dissipation lower than a microampere, a phase comparator measuring the phase error between the divided frequency signal Fout1/n and the reference signal and being able to produce a test signal, a low-pass filter or an integrating circuit able to filter the test signal and able to generate a voltage or a control word designed to control the voltage-controlled or digitally controlled oscillator.

Abstract: Time base including two oscillators, one of which has a lower frequency than the other, the latter being intermittently set to standby mode, generating according to the same intermittency a first stable time reference (REF) by difference between the frequencies of the two oscillators, a second permanent time reference (RTC) being obtained by division of the frequency of the oscillator having the lowest frequency and the division factor being dependent on the pulses counted for the first oscillator (OSC1) during a time interval determined by the first stable time reference (REF).

Abstract: This clock generator comprises an oscillator for generating an alternating current pilot signal and a pulse formatting circuit which is intended to convert the pilot signal from the oscillator into a pulse clock signal having a duty factor of at least approximately 50%. According to one implementation, a series of at least two inverters is provided, the input of the first inverter being controlled by the alternating current pilot signal and the output of the second inverter supplying the clock signal. A power supply means may also be provided to supply the inverters with a regulated power supply voltage dependent on the signals appearing at the outputs of the inverters.

Abstract: Time base including two oscillators, one of which has a lower frequency than the other, the latter being intermittently set to standby mode, generating according to the same intermittency a first stable time reference (REF) by difference between the frequencies of the two oscillators, a second permanent time reference (RTC) being obtained by division of the frequency of the oscillator having the lowest frequency and the division factor being dependent on the pulses counted for the first oscillator (OSC1) during a time interval determined by the first stable time reference (REF).

Abstract: This clock generator comprises an oscillator for generating an alternating current pilot signal and a pulse formatting circuit which is intended to convert the pilot signal from the oscillator into a pulse clock signal having a duty factor of at least approximately 50%. According to one implementation, a series of at least two inverters is provided, the input of the first inverter being controlled by the alternating current pilot signal and the output of the second inverter supplying the clock signal. A power supply means may also be provided to supply the inverters with a regulated power supply voltage dependent on the signals appearing at the outputs of the inverters.