Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

Abstract: A method and apparatus for a wireless transmit receive unit (WTRU) to use a contention-based uplink communications channel, applies a rule-based restriction of access to the contention-based uplink channel that attempts to use at least one contention-free uplink channel allocation for uplink transmissions on a condition that at least one contention-free uplink channel allocation has been granted.

Abstract: A method and apparatus are described for obtaining port index information. In one scenario, downlink (DL) control information (DCI) is received that includes new data indicator (NDI). The NDI has a value indicating an antenna port for single-port transmission. In response to receiving the DCI, a single-port transmission associated with the indicated antenna port is received. The NDI may be associated with a disabled codeword and the DCI may include a second NDI. The DCI may be received over a physical downlink control channel (PDCCH). The DCI may include a resource block (RB) assignment information field (IF), a hybrid automatic repeat request (HARQ) process identity (ID) IF, a transmit power control (TPC) IF and, for each of a plurality of transport blocks, a modulation and coding scheme (MCS), an NDI and a redundancy version (RV).

Abstract: A Node-B/base station has an access burst detector. The access burst detector comprises at least one antenna for receiving signals from users and a pool of reconfigurable correlators. Each correlator correlates an inputted access burst code at an inputted code phase with an inputted antenna output. An antenna controller selectively couples any output of the at least one antenna to an input of any of the correlators. A code controller provides to an input of each correlator an access burst code. The code controller controls the inputted code phase of each controller. A sorter/post processor sorts output energy levels of the correlators.

Abstract: A method and apparatus for optimization of a modem for high data rate applications comprise a plurality of hardware accelerators which are configured to perform data processing functions, wherein the hardware accelerators are parameterized, a processor is configured to selectively activate accelerators according to the desired function to conserve power requirements and a shared memory configured for communication between the plurality of hardware accelerators.

Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

Abstract: An iterative turbo decoder for a wireless transmit receive unit (WTRU) of a wireless communication system and method for error correcting received communication signal data are provided. The decoder implements a stopping rule through use of signature codes to determine whether successive iterations of decoder data are the same.

Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

Abstract: An iterative turbo decoder for a wireless transmit receive unit (WTRU) of a wireless communication system and method for error correcting received communication signal data are provided. The decoder implements a stopping rule through use of signature codes to determine whether successive iterations of decoder data are the same.

Abstract: A Node-B/base station receiver comprises at least one antenna for receiving signals. Each finger of a pool of reconfigurable Rake fingers recovers a multipath component of a user and is assigned a code of the user, a code phase of the multipath component and an antenna of the at least one antenna. An antenna/Rake finger pool interface provides each finger of the Rake pool an output of the antenna assigned to that Rake finger. A combiner combines the recovered multipath components for a user to produce data of the user.

Abstract: A Node-B/base station has a path searcher and at least one antenna for receiving signals from users. The path searcher comprises a set of correlators. Each correlator correlates an inputted user code with an inputted antenna output of the at least one antenna. An antenna controller selectively couples any output of the at least one antenna to an input of each correlator of the set of correlators. A code phase controller selects a user code for input into the set of correlators. Each delay of a series of delays delays the selected user code by a predetermined amount and each correlator of the set of correlators receives a different code phase delay of the selected user code. A sorter and path selector sorts the output energy levels of each correlator of the sets of correlators and produces a path profile for a user based on the sorted output energy levels.

Abstract: A Node-B/base station receiver comprises at least one antenna for receiving signals. Each finger of a pool of reconfigurable Rake fingers recovers a multipath component of a user and is assigned a code of the user, a code phase of the multipath component and an antenna of the at least one antenna. An antenna/Rake finger pool interface provides each finger of the Rake pool an output of the antenna assigned to that Rake finger. A combiner combines the recovered multipath components for a user to produce data of the user.

Abstract: A Node-B/base station receiver comprises at least one antenna for receiving signals. Each finger of a pool of reconfigurable Rake fingers recovers a multipath component of a user and is assigned a code of the user, a code phase of the multipath component and an antenna of the at least one antenna. An antenna/Rake finger pool interface provides each finger of the Rake pool an output of the antenna assigned to that Rake finger. A combiner combines the recovered multipath components for a user to produce data of the user.

Abstract: A Node-B/base station has a path searcher and at least one antenna for receiving signals from users. The path searcher comprises a set of correlators. Each correlator correlates an inputted user code with an inputted antenna output of the at least one antenna. An antenna controller selectively couples any output of the at least one antenna to an input of each correlator of the set of correlators. A code phase controller selects a user code for input into the set of correlators. Each delay of a series of delays delays the selected user code by a predetermined amount and each correlator of the set of correlators receives a different code phase delay of the selected user code. A sorter and path selector sorts the output energy levels of each correlator of the sets of correlators and produces a path profile for a user based on the sorted output energy levels.

Abstract: A Node-B/base station has an access burst detector. The access burst detector comprises at least one antenna for receiving signals from users and a pool of reconfigurable correlators. Each correlator correlates an inputted access burst code at an inputted code phase with an inputted antenna output. An antenna controller selectively couples any output of the at least one antenna to an input of any of the correlators. A code controller provides to an input of each correlator an access burst code. The code controller controls the inputted code phase of each controller. A sorter/post processor sorts output energy levels of the correlators.

Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

Abstract: An apparatus for testing digital logic circuits without a computer and associated software employs a psuedorandom stream of input data to produce an unstructured output data stream which is analyzed by an efficient data collector and analyzer. Test signal generation is implemented by a pseudorandom number generator and a pseudorandom clock/reset generator while the resulting test data at the output terminals of the device under test is analyzed by a cycle redundancy code checker. Fault localization is realized, with selectable localization and manual probe modes and circuitry is provided for an efficient self-test mode.

Abstract: An apparatus for testing digital logic circuits without a computer and associated software employs a pseudorandom stream of input data to produce an unstructured output data stream which is analyzed by an efficient data collector and analyzer. Test signal generation is implemented by a pseudorandom number generator and a pseudorandom clock/reset generator while the resulting test data at the output terminals of the device under test is analyzed by a cycle redundancy code checker. Fault localization is realized, with selectable localization and manual probe modes and circuitry is provided for an efficient self-test mode.