Patents by Inventor David S. Broomhead

David S. Broomhead has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5845123
    Abstract: A digital processor for simulating operation of a parallel processing array incorporates digital processing units (P.sub.1 to P.sub.8) communicating data to one another via addresses in memories (M.sub.0 to M.sub.8) and registers (R.sub.11 to R.sub.41). Each processing unit (e.g. P.sub.1) is programmed to input data and execute a computation involving updating of a stored coefficient followed by data output. Each computation involves use of a respective set of data addresses for data input and output, and each processing unit (e.g. P.sub.1) is programmed with a list of such sets employed in succession by that unit. On reaching the end of its list, the processing unit (e.g. P.sub.1) repeats it. Each address set is associated with a conceptual internal cell location in the simulated array (10), and each list is associated with a respective sub-array of the simulated array (10). Data is input cyclically to the processor (40) via input/output ports (I/O.sub.5 to I/O.sub.8) of some of the processing units (P.sub.
    Type: Grant
    Filed: February 12, 1993
    Date of Patent: December 1, 1998
    Assignee: The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventors: Martin Johnson, Robin Jones, David S. Broomhead
  • Patent number: 5835682
    Abstract: A dynamical system analyser (10) incorporates a computer (22) to perform a singular value decomposition of a time series of signals from a nonlinear (possibly chaotic) dynamical system (14). Relatively low-noise singular vectors from the decomposition are loaded into a finite impulse response filter (34). The time series is formed into Takens' vectors each of which is projected onto each of the singular vectors by the filter (34). Each Takens' vector thereby provides the co-ordinates of a respective point on a trajectory of the system (14) in a phase space. A heuristic processor (44) is used to transform delayed co-ordinates by QR decomposition and least squares fitting so that they are fitted to non-delayed co-ordinates. The heuristic processor (44) generates a mathematical model to implement this transformation, which predicts future system states on the basis of respective current states. A trial system is employed to generate like co-ordinates for transformation in the heuristic processor (44).
    Type: Grant
    Filed: November 1, 1995
    Date of Patent: November 10, 1998
    Assignee: The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventors: David S. Broomhead, Robin Jones, Martin Johnson
  • Patent number: 5493516
    Abstract: A dynamical system analyzer (10) incorporates a computer (22) to perform a singular value decomposition of a time series of signals from a nonlinear (possibly chaotic) dynamical system (14). Relatively low-noise singular vectors from the decomposition are loaded into a finite impulse response filter (34). The time series is formed into Takens' vectors each of which is projected onto each of the singular vectors by the filter (34). Each Takens' vector thereby provides the co-ordinates of a respective point on a trajectory of the system (14) in a phase space. A heuristic processor (44) is used to transform delayed co-ordinates by QR decomposition and least squares fitting so that they are fitted to non-delayed co-ordinates. The heuristic processor (44) generates a mathematical model to implement this transformation, which predicts future system states on the basis of respective current states. A trial system is employed to generate like co-ordinates for transforation in the heuristic processor (44).
    Type: Grant
    Filed: March 14, 1995
    Date of Patent: February 20, 1996
    Assignee: The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventors: David S. Broomhead, Robin Jones, Martin Johnson
  • Patent number: 5475793
    Abstract: A heuristic processor incorporates a digital arithmetic unit arranged to compute the squared norm of each member of a training data set with respect to each member of a set of centers, and to transform the squared norms in accordance with a non-linear function to produce training .phi. vectors. A systolic array arranged for QR decomposition and least means squares processing forms combinations of the elements of each .phi. vector to provide a fit to corresponding training answers. The form of combination is then employed with like-transformed test data to provide estimates of unknown results. The processor is applicable to provide estimated results for problems which are non-linear and for which explicit mathematical formalisms are unknown.
    Type: Grant
    Filed: May 2, 1994
    Date of Patent: December 12, 1995
    Assignee: The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventors: David S. Broomhead, Robin Jones, Terence J. Shepherd, John G. McWhirter
  • Patent number: 5453940
    Abstract: A dynamical system analyser (10) incorporates a computer (22) to perform a singular value decomposition of a time series of signals from a nonlinear (possibly chaotic) dynamical system (14). Relatively low-noise singular vectors from the decomposition are loaded into a finite impulse response filter (34). The time series is formed into Takens' vectors each of which is projected onto each of the singular vectors by the filter (34). Each Takens' vector thereby provides the co-ordinates of a respective point on a trajectory of the system (14) in a phase space. A heuristic processor (44) is used to transform delayed co-ordinates by QR decomposition and least squares fitting so that they are fitted to non-delayed co-ordinates. The heuristic processor (44) generates a mathematical model to implement this transformation, which predicts future system states on the basis of respective current states. A trial system is employed to generate like co-ordinates for transforation in the heuristic processor (44).
    Type: Grant
    Filed: October 7, 1993
    Date of Patent: September 26, 1995
    Assignee: The Secretary of the State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventors: David S. Broomhead, Robin Jones, Martin Johnson
  • Patent number: 5377306
    Abstract: A heuristic processor incorporates a digital arithmetic unit arranged to compute the squared norm of each member of a training data set with respect to each member of a set of centers, and to transform the squared norms in accordance with a nonlinear function to produce training .phi. vectors. A systolic array arranged for QR decomposition and least mean squares processing forms combinations of the elements of each .phi. vector to provide a fit to corresponding training answers. The form of combination is then employed with like-transformed test data to provide estimates of unknown results. The processor is applicable to provide estimated results for problems which are nonlinear and for which explicit mathematical formalisms are unknown.
    Type: Grant
    Filed: September 12, 1991
    Date of Patent: December 27, 1994
    Assignee: The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventors: David S. Broomhead, Robin Jones, Terence J. Shepherd, John G. McWhirter