Abstract: Disclosed herein are integrated circuit devices having stacked power supplies and methods of making such integrated circuit devices. In one example, the device includes a first power supply structure, a second power supply structure electrically isolated from the first power supply structure, wherein at least a portion of the second power supply structure is positioned vertically below at least a portion of the first power supply structure, wherein the first power supply structure is one of an interruptible or an uninterruptible power supply structure, while the second power supply structure is the other of the interruptible or the uninterruptible power supply structure, a plurality of constant-power circuits conductively coupled to whichever of the first or second power supply structure that is the uninterruptible power supply and a plurality of interruptible-power circuits conductively coupled to whichever of the first or second power supply structure that is the interruptible power supply.

Abstract: A computer-readable software product is provided for executing a method of determining the location of a plurality of power rail vias in a semiconductor device. The semiconductor device includes an active region and a power rail. Locations of a first via and a second via are assigned along the power rail. The spacing between the location of the first via and the location of the second via is a minimum spacing allowable. The spacing between the location of the second via and the locations of structures in the active region which may electrically interfere with the second via is determined. The location of the second via is changed in response to the spacing between the location of the second via and the location of one of the structures in the active region being less than a predetermined distance.

Abstract: A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.

Abstract: A computer-readable software product is provided for executing a method of determining the location of a plurality of power rail vias in a semiconductor device. The semiconductor device includes an active region and a power rail. Locations of a first via and a second via are assigned along the power rail. The spacing between the location of the first via and the location of the second via is a minimum spacing allowable. The spacing between the location of the second via and the locations of structures in the active region which may electrically interfere with the second via is determined. The location of the second via is changed in response to the spacing between the location of the second via and the location of one of the structures in the active region being less than a predetermined distance.

Abstract: A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.

Abstract: Disclosed herein are integrated circuit devices having stacked power supplies and methods of making such integrated circuit devices. In one example, the device includes a first power supply structure, a second power supply structure electrically isolated from the first power supply structure, wherein at least a portion of the second power supply structure is positioned vertically below at least a portion of the first power supply structure, wherein the first power supply structure is one of an interruptible or an uninterruptible power supply structure, while the second power supply structure is the other of the interruptible or the uninterruptible power supply structure, a plurality of constant-power circuits conductively coupled to whichever of the first or second power supply structure that is the uninterruptible power supply and a plurality of interruptible-power circuits conductively coupled to whichever of the first or second power supply structure that is the interruptible power supply.

Abstract: Disclosed herein are various methods and circuits for achieving rational fractional drive strengths in circuits employing FinFET devices. In one example, the device disclosed herein includes a semiconducting substrate, a first plurality of FinFET transistors formed in and above the substrate, wherein each of the first plurality of FinFET transistors is adapted to produce an individual drive current, and wherein the first plurality of FinFET transistors are configured in a series circuit. The drive current resulting from the series circuit is a rational fraction of the individual drive current.