Abstract: Bulk data is read or written by an application on a first computer system to a file on a second heterogeneous computer system. Alternatively it is read or written as bulk data directly between applications on these heterogeneous systems. Jobs or tasks are started from one system to execute on a second heterogeneous system. Results are then returned to the first system. Checkpointing and later restarting is also initiated from a first system for execution on the second heterogeneous system.

Abstract: Bulk data is read or written by an application on a first computer system to a file on a second heterogeneous computer system. Alternatively it is read or written as bulk data directly between applications on these heterogeneous systems. Jobs or tasks are started from one system to execute on a second heterogeneous system. Results are then returned to the first system. Checkpointing and later restarting is also initiated from a first system for execution on the second heterogeneous system.

Abstract: A system and method that enhances the data access performance of a multi-layer relational database manager by expanding the code generation component layer of the database manager to include a number of performance enhancing subroutines designed to execute functions performed by lower component layers substantially faster than if the functions were executed by such lower component layers. Each such subroutine includes logic for establishing the conditions under which the particular subroutine is invoked during the processing of a SQL request. During process of generating code for a specific SQL query, the code generation component layer inserts calls to the different performance enhancing subroutines in place of normally included calls to lower component layers. This results in the insertion of the different performance enhancing subroutines into the generated code.

Abstract: A system and method that enhances the row retrieval performance of a multi-layer relational database manager by including in the code generation component layer of the database manager a row retrieval performance enhancing subroutine designed to execute functions performed by a lower component layer substantially faster than if the functions were executed by such lower component layer. The subroutine includes logic for establishing the conditions under which the particular subroutine is invoked during the execution of a SQL request. The output code generated to execute a specific SQL query, including calls to the row retrieval subroutine in place of normally included calls to the lower component layer. This enables the generated code to perform lower component layer functions with specialized code designed to increase performance based on the characteristics of the data being retrieved.

Abstract: A system and method that enhances the index processing performance of a multi-layer relational database manager by expanding the code generation component layer of the database manager to include an index processing performance enhancing subroutine designed to execute functions performed by lower component layers substantially faster than if the functions were executed by such lower component layers. The subroutine includes logic for establishing the conditions under which the particular subroutine is invoked during the execution of a SQL request. The output code generated to execute a specific SQL query, including calls to the index processing subroutine in place of normally included calls to the lower component layer. This enables the generated code to perform lower component layer functions with specialized code designed to increase performance.

Abstract: A fault tolerant computer system includes at least two central processing units each having a cache memory and a parity error detector adapted to sense parity errors in blocks of information read from and write to cache and to issue a cache parity read or write error flag if a parity error is sensed. A system bus couples the CPU to a System Control Unit having a parity error correction facility, and a memory bus couples the SCU to a main memory. An error recovery control feature distributed across the CPU, including a Service Processor and the operating system software, is responsive to the sensing of a read parity error flag in a sending CPU and a write parity error flag in a receiving CPU in conjunction with a siphon operation for transferring the faulting block from the sending CPU to main memory via the SCU (in which given faulting block is corrected) and for subsequently transferring the corrected memory block from main memory to the receiving CPU when a retry is instituted.

Abstract: Dense star polymer conjugates which are composed of at least one dendrimer in association with at least one unit of a carried agricultural, pharmaceutical, or other material have been prepared. These conjugates have particularly advantageous properties due to the unique characteristics of the dendrimer.

Abstract: Tris(isonitrile)copper(I) sulfate complexes and their use in synthetic methods for making radionuclide isonitrile coordination complexes such as [.sup.99m Tc(1-isocyano-2-methoxy-2-methylpropane).sub.6 ].sup.+. The coordination complexes are useful as radiopharmaceutical imaging agents.

Abstract: Disclosed are cationic complexes of Tc-99m and ligands having the structure: ##STR1## wherein: R.sup.1 is hydrogen or is selected from the group consisting of C.sub.1 to C.sub.20 alkyl; C.sub.3 to C.sub.12 cycloalkyl; C.sub.7 to C.sub.24 aralkyl; C.sub.2 to C.sub.16 alkyl ethers, thioethers, ketones or esters; C.sub.7 to C.sub.27 aralkyl ethers;R.sup.2 is hydrogen or is a C.sub.1 to C.sub.4 lower alkyl radical selected from the group consisting of methyl, ethyl, propyl, isopropyl, butyl, isobutyl, sec-butyl and tert-butyl.

Abstract: In order to gather, store temporarily and deliver (if needed) central processor safestore information, a multiphase clock is employed to capture (one full clock cycle behind) the safestore information which typically includes all software visible registers in all (or selected) data manipulation chips of the CPU by routing the safestore information through temporary storage (under the influence of the multiphase clock) in a cache data array and into a special purpose XRAM module. Thus, upon the sensing of a fault, valid safestore information is available in the XRAM for analysis and, if appropriate, resumption of operation at a sequential point just previous to that at which the fault occurred.

Abstract: In order to provide efficient error detection in a central processor's Basic Processing Unit (BPU) including an AX (address and execution) module, a DN (decimal numeric) module and an FP (floating point) module, each module is provided redundantly in a master/slave pair, and the local result of data manipulation operations performed in each pair are compared for identity before the results are validated for subsequent use in the central processor.

Abstract: In a computer system having a hardware and/or firmware design problem which causes a false boundary error under certain conditions, the subject method serves to handle and correct the false boundary error condition in the operating system. This recovery process is carried out such that the information from which the faulting address was developed is redistributed among a plurality of information components in such a manner that the false boundary error will not recur on retry. Thus, the process masks the problem by remapping the virtual address components of the faulting instruction so that the final virtual address, though identical to the failing one, is processed without fault by the central processor unit during recovery.

Abstract: Apparatus is disclosed for incorporation in a central processing unit that permits a testing procedure to be executed on the central processing unit in a manner that simulates the normal operation of the central processing unit. The apparatus includes an auxiliary memory unit, in which the test programs are stored, and an auxiliary processor for controlling the central processing unit when the test procedure is initiated and for preparing the central processing unit for execution of the test procedures. Control apparatus of the central processing unit executes the test program retrieved from the auxiliary memory unit. The auxiliary processor regains control of the central processing unit after the test program has been executed, tests the results of the test procedure and returns control to the central processing unit.