Abstract: A memory structure which can operate as a stack or list, the structure comprising a plurality of contiguous memory locations sub-divided into contiguous sub-structures, each of the sub-structures having at least one buffer memory location associated with it, whereby stack or list shuffle operations can be performed in parallel on the sub-structures. The memory structure can be utilized in a content addressable memory and records can be maintained in sorted order by key in the memory structure. The content addressable memory can be implemented using currently available random access memory (RAM) structures and the content addressable memory can be implemented in very large scale integration (VLSI).