Abstract: Some embodiments include an integrated assembly having first conductive structures extending along a first direction. Spaced-apart upwardly-opening container-shapes are over the first conductive structures. Each of the container-shapes has a first sidewall region, a second sidewall region, and a bottom region extending from the first sidewall region to the second sidewall region. Each of the first and second sidewall regions includes a lower source/drain region, an upper source/drain region, and a channel region between the upper and lower source/drain regions. The lower source/drain regions are electrically coupled with the first conductive structures. Second conductive structures extend along a second direction which crosses the first direction. The second conductive structures have gate regions operatively adjacent the channel regions. Storage elements are electrically coupled with the upper source/drain regions. Some embodiments include methods of forming integrated assemblies.

Abstract: A dual mode memory interface includes a bus switch and a register/buffer operatively coupled to the bus switch. The dual mode memory interface may include, operatively coupled to the bus switch and the register/buffer, enable/disable pins configured so that only one of the bus switch and the register/buffer is active at a time. The bus switch may be a transistor configured as a pass gate. The dual mode memory interface may be implemented in a single integrated circuit package. The dual mode memory interface may further include a system controller for detecting a type of memory module connected to the dual mode memory interface and enabling one of the bus switch and register/buffer based on the type of memory module detected.

Abstract: A dual mode memory module includes an interface configured to receive a first memory module, a first control circuit for switching between unbuffered and registered/buffered modes, an interface configured to receive a second memory module, and a second control circuit for switching the operation of the second memory module between unbuffered and registered/buffered modes. The control circuit may include a bus switch and a register/buffer operatively coupled to the bus switch. Enable/disable pins may be included operatively coupled to the first bus switch and the first register/buffer and configured so that only one of the first bus switch and the first register/buffer is active at a time. A system controller for detecting a type of memory module connected to the stackable dual mode memory interface and enabling one of the bus switch and register/buffer based on the type of memory module detected may be included.

Abstract: A device for automatically varying resistance includes a comparator for comparing a control voltage to a reference voltage; a switch operatively coupled to the comparator; and a first resistor and second resistor operatively coupled in a series connection between a pull-up voltage and a signal line. The switch is operatively coupled in a parallel connection with the first resistor and, based on the comparison between the control voltage and the reference voltage, the switch selectively bypasses the first resistor. A method of automatically varying resistance includes comparing a control voltage and a reference voltage; pulling-up a signal line to a pull-up voltage through a first resistor and a second resistor operatively connected in series if the comparison has a first outcome; and pulling up the signal line to the pull-up voltage through only the second resistor if the comparison has a second outcome.

Abstract: A device for automatically providing variable resistance includes a comparator for comparing a reference voltage to an operating voltage, a first switch operatively coupled to the comparator, a first resistor operatively coupled with the first switch in a series connection between a pull-up voltage and a signal line, a second switch operatively coupled to the comparator, and a second resistor operatively coupled in a series connection with the second switch between the pull-up voltage and the signal line. The first switch selectively electrically enables the connection between the pull-up voltage and the signal line through the first resistor based on the comparison between the reference voltage and the operating voltage and the second switch selectively electrically enables the connection between the pull-up voltage and the signal line through the second resistor based on the comparison between the reference voltage and operating voltage.

Abstract: An intelligent power module includes a power supply, control circuitry controlling whether power is delivered by the power supply and a controller that determines a status of the power supply and instructs the control circuitry to control whether power is delivered by the power supply based on the status of the power supply. A method of intelligently supplying power includes determining a state of a power supply and selectively turning on the power supply based on the state of the power supply. An intelligent power delivery system includes a backplane, a system management controller residing on the backplane, and a power module operatively coupled to the backplane. The system management controller monitors a state of the power module prior to powering on the power module.

Abstract: A data processing apparatus is described which comprises a microprocessor having data lines, address lines and control lines, a memory interface having input control lines, input address lines, output control lines, and output I/O lines wherein one or more input address lines of the memory interface are coupled to an equal number of address lines of the microprocessor. Further, a memory having control lines and I/O lines is provided, the control lines of the memory being coupled to output control lines of the memory interface, and I/O lines of the memory being coupled to output I/O lines of the memory interface. The memory receives command, data and address information through the I/O lines.