Abstract: Techniques that facilitate model support in deep learning are provided. In one example, a system includes a graphics processing unit and a central processing unit memory. The graphics processing unit processes data to train a deep neural network. The central processing unit memory stores a portion of the data to train the deep neural network. The graphics processing unit provides, during a forward pass process of the deep neural network that traverses through a set of layers for the deep neural network from a first layer of the set of layers to a last layer of the set of layers that provides a set of outputs for the deep neural network, input data for a layer from the set of layers for the deep neural network to the central processing unit memory.

Abstract: Techniques that facilitate model support in deep learning are provided. In one example, a system includes a graphics processing unit and a central processing unit memory. The graphics processing unit processes data to train a deep neural network. The central processing unit memory stores a portion of the data to train the deep neural network. The graphics processing unit provides, during a forward pass process of the deep neural network that traverses through a set of layers for the deep neural network from a first layer of the set of layers to a last layer of the set of layers that provides a set of outputs for the deep neural network, input data for a layer from the set of layers for the deep neural network to the central processing unit memory.

Abstract: Techniques for image processing and transformation are provided. A plurality of images and a plurality of maps are received, and a system of neural networks is trained based on the plurality of images and the plurality of maps. A first image is received, and a first map is generated by processing the first image using the system of neural networks.

Abstract: Techniques that facilitate model support in deep learning are provided. In one example, a system includes a graphics processing unit and a central processing unit memory. The graphics processing unit processes data to train a deep neural network. The central processing unit memory stores a portion of the data to train the deep neural network. The graphics processing unit provides, during a forward pass process of the deep neural network that traverses through a set of layers for the deep neural network from a first layer of the set of layers to a last layer of the set of layers that provides a set of outputs for the deep neural network, input data for a layer from the set of layers for the deep neural network to the central processing unit memory.

Abstract: Techniques regarding a zero-confidence adversarial attack are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an adversarial component that computes a perturbation that causes misclassification by a neural network classifier. The computer executable components can also comprise a restoration component that determines a normal vector to a constraint contour developed by the neural network classifier. Further, the computer executable components can comprise a projection component that determines a tangential vector to the constraint contour.

Abstract: Techniques for image processing and transformation are provided. A plurality of images and a plurality of maps are received, and a system of neural networks is trained based on the plurality of images and the plurality of maps. A first image is received, and a first map is generated by processing the first image using the system of neural networks.

Abstract: A method for executing multi-directional reduction algorithms includes identifying a set of nodes, wherein a node includes at least one data element, creating a set of partitions including one or more data elements from at least two nodes, wherein the at least two nodes are arranged in a single direction with respect to the positioning of the set of nodes, executing a reduction algorithm on the data elements within the created set of partitions, creating an additional set of partitions including one or more data elements from at least two nodes, wherein the at least two nodes are arranged in a different direction with respect to the positioning of the set of nodes, executing a reduction algorithm on the data elements within the created additional set of partitions, and providing a set of reduced results corresponding to the at least one data element.

Abstract: Techniques regarding a zero-confidence adversarial attack are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an adversarial component that computes a perturbation that causes misclassification by a neural network classifier. The computer executable components can also comprise a restoration component that determines a normal vector to a constraint contour developed by the neural network classifier. Further, the computer executable components can comprise a projection component that determines a tangential vector to the constraint contour.

Abstract: Techniques that facilitate model support in deep learning are provided. In one example, a system includes a graphics processing unit and a central processing unit memory. The graphics processing unit processes data to train a deep neural network. The central processing unit memory stores a portion of the data to train the deep neural network. The graphics processing unit provides, during a forward pass process of the deep neural network that traverses through a set of layers for the deep neural network from a first layer of the set of layers to a last layer of the set of layers that provides a set of outputs for the deep neural network, input data for a layer from the set of layers for the deep neural network to the central processing unit memory.

Abstract: A method for executing multi-directional reduction algorithms includes identifying a set of nodes, wherein a node includes at least one data element, creating a set of partitions including one or more data elements from at least two nodes, wherein the at least two nodes are arranged in a single direction with respect to the positioning of the set of nodes, executing a reduction algorithm on the data elements within the created set of partitions, creating an additional set of partitions including one or more data elements from at least two nodes, wherein the at least two nodes are arranged in a different direction with respect to the positioning of the set of nodes, executing a reduction algorithm on the data elements within the created additional set of partitions, and providing a set of reduced results corresponding to the at least one data element.

Abstract: Determining optimum values for Map Reduce parameters by identifying parameters that affect performance of a Map Reduce job, determining a relationship between each of the identified parameters and a maximization of resource utilization for a plurality of computing resources configured for executing the Map Reduce job, representing a workflow based upon supply-demand relationships among the plurality of computing resources, modeling an execution cost as a function of the plurality of identified parameters, formulating a non-linear programming problem to minimize the execution cost, reformulating the non-linear programming problem as a linear programming problem, and solving the linear programming problem to determine a combination of parameter values for the plurality of identified parameters that minimizes the execution cost for the Map Reduce job.

Abstract: Determining optimum values for Map Reduce parameters by identifying parameters that affect performance of a Map Reduce job, determining a relationship between each of the identified parameters and a maximization of resource utilization for a plurality of computing resources configured for executing the Map Reduce job, representing a workflow based upon supply-demand relationships among the plurality of computing resources, modeling an execution cost as a function of the plurality of identified parameters, formulating a non-linear programming problem to minimize the execution cost, reformulating the non-linear programming problem as a linear programming problem, and solving the linear programming problem to determine a combination of parameter values for the plurality of identified parameters that minimizes the execution cost for the Map Reduce job.

Abstract: In one embodiment, the invention is a method and apparatus for variation enabling statistical testing using deterministic multi-corner timing analysis. One embodiment of a method for obtaining statistical timing data for an integrated circuit chip includes obtaining deterministic multi-corner timing data for the integrated circuit chip and constructing the statistical timing data from the deterministic multi-corner timing data.

Abstract: In one embodiment, the invention is a method and apparatus for variation enabling statistical testing using deterministic multi-corner timing analysis. One embodiment of a method for obtaining statistical timing data for an integrated circuit chip includes obtaining deterministic multi-corner timing data for the integrated circuit chip and constructing the statistical timing data from the deterministic multi-corner timing data.

Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Abstract: An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.

Abstract: An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.

Abstract: A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.

Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Abstract: A method, system and program product are described for generating a clock distribution network on an integrated circuit by determining an allowable placement region for each of a set of clock tree leaf elements in the integrated circuit. This allowable placement region is generated by determining and intersecting a set of sub-regions under different constraints, each of which identifies an area in which the clock tree leaf element is placed to satisfy the respective constraint. Constraints for which sub-regions are determined include timing constraints in the form of slacks and congestion constraints. After allowable placement regions have been determined, the clock tree leaf elements are clustered, and each clock tree leaf element is placed at a location within its allowable placement region which minimizes some cost function for that clustering.