Abstract: A microprocessor includes a decode unit that maps architectural instructions into micro-operations and dispatches them to a scheduler that issues them to execution units that execute them by reading source operands from a register file and writing execution results to the register file. An architectural instruction instructs the microprocessor to load a constant into an architectural destination register. The decode unit maps the architectural instruction into a load constant micro-operation (LCM) and writes the LCM constant directly to a register of the register file without dispatching the LCM to the scheduler, such that the LCM is not issued to the execution units. In the same clock cycle, the decode unit indicates the LCM constant is available for consumption, such that the LCM imposes zero execution latency on dependent micro-operations and dispatches to the scheduler micro-operations other than the LCM. The register file may include a decode unit-dedicated write port.

Abstract: A processor for mitigating side channel attacks includes units that perform fetch, decode, and execution of instructions and pipeline control logic. The processor performs speculative and out-of-order execution of the instructions. The units detect and notify the control unit of events that cause a change from a first translation context (TC) to a second TC. In response, the pipeline control logic prevents speculative execution of instructions that are dependent in their execution on the change to the second TC until all instructions that are dependent on the first TC have completed execution, which may involve stalling their dispatch until all first-TC-dependent instructions have at least completed execution, or by tagging them and dispatching them to execution schedulers but preventing them from starting execution until all first-TC-dependent instructions have at least completed execution.

Abstract: A processor for mitigating side channel attacks includes units that perform fetch, decode, and execution of instructions and pipeline control logic. The processor performs speculative and out-of-order execution of the instructions. The units detect and notify the control unit of events that cause a change from a first translation context (TC) to a second TC. In response, the pipeline control logic prevents speculative execution of instructions that are dependent in their execution on the change to the second TC until all instructions that are dependent on the first TC have completed execution, which may involve stalling their dispatch until all first-TC-dependent instructions have at least completed execution, or by tagging them and dispatching them to execution schedulers but preventing them from starting execution until all first-TC-dependent instructions have at least completed execution.

Abstract: Various aspects provide for mitigating voltage droop associated with a microprocessor (e.g., by controlling a clock associated with the microprocessor). For example, a system can include a microprocessor and a controller. The microprocessor can receive a clock provided by a clock buffer. The controller can control frequency of the clock provided by the clock buffer based on a voltage associated with the microprocessor. In an aspect, the controller can reduce the frequency of the clock in response to a determination that the voltage satisfies a defined criterion. Additionally, the controller can incrementally increase the frequency of the clock in response to another determination that the voltage satisfies another defined criterion after satisfying the defined criterion.

Abstract: A device and methods are disclosed for communicating an unrounded result from one arithmetic calculation for use in a second, subsequent calculation. For example, an unrounded result of a first calculation can be forwarded to provide a multiplier, a multiplicand or an addend operand for the subsequent operation. The operand can be forwarded to the input of the same fused multiply addition module (FMAM) that supplied the result, or to another FMAM, and do so without regard to the precision of the forwarded operand, the precision of the subsequent operation, or the native precision of the FMAM.

Abstract: A device and methods are disclosed for communicating an unrounded result from one arithmetic calculation for use in a second, subsequent calculation. For example, an unrounded result of a first calculation can be forwarded to provide a multiplier, a multiplicand or an addend operand for the subsequent operation. The operand can be forwarded to the input of the same fused multiply addition module (FMAM) that supplied the result, or to another FMAM, and do so without regard to the precision of the forwarded operand, the precision of the subsequent operation, or the native precision of the FMAM.

Abstract: A floating point unit includes a floating point adder to perform a floating point addition operation between first and second floating point numbers each having an exponent and a mantissa. The floating point unit also includes an alignment shifter that may calculate a shift value corresponding to a number of bit positions to shift the second mantissa such that the second exponent value is the same as the first exponent value. The alignment shifter may detect an overshift condition, in which the shift value is greater than or equal to a selected overshift threshold value. The selected overshift threshold value comprises a base 2 number in a range of overshift values including a minimum overshift threshold value and a maximum overshift threshold value, and which has a largest number of a consecutive of bits that are zero beginning at a least significant bit.

Abstract: A floating point unit includes a floating point adder to perform a floating point addition operation between first and second floating point numbers each having an exponent and a mantissa. The floating point unit also includes an alignment shifter that may calculate a shift value corresponding to a number of bit positions to shift the second mantissa such that the second exponent value is the same as the first exponent value. The alignment shifter may detect an overshift condition, in which the shift value is greater than or equal to a selected overshift threshold value. The selected overshift threshold value comprises a base 2 number in a range of overshift values including a minimum overshift threshold value and a maximum overshift threshold value, and which has a largest number of a consecutive of bits that are zero beginning at a least significant bit.

Abstract: A device and methods are disclosed for communicating an unrounded result from one arithmetic calculation for use in a second, subsequent calculation. For example, an unrounded result of a first calculation can be forwarded to provide a multiplier, a multiplicand or an addend operand for the subsequent operation. The operand can be forwarded to the input of the same fused multiply addition module (FMAM) that supplied the result, or to another FMAM, and do so without regard to the precision of the forwarded operand, the precision of the subsequent operation, or the native precision of the FMAM.

Abstract: An arithmetic processing unit is disclosed that can perform multiply operations, addition operations, or a combination thereof. The arithmetic processing unit can operate in two modes. The first mode supports one single, double, or extended-precision computation, and the second mode supports two simultaneous single-precision computations using the same exponent and mantissa datapaths.

Abstract: A variable speed floating point unit comprising: 1) an execution pipeline comprising a plurality of execution stages capable of executing floating point operations in a series of sequential steps; and 2) a clock controller capable of receiving an input clock signal and generating a variable speed output clock signal capable of clocking the execution pipeline. The clock controller adjusts a speed of the variable speed output clock signal according to a level of queued opcodes waiting to be executed in the execution pipeline.

Abstract: An apparatus and method is disclosed for updating a status register in an out of order execution pipeline. In one embodiment a dispatch unit in a floating point unit sets a MRI bit flag that indicates that an instruction is the most recently issued instruction. The dispatch unit resets the MRI bit flag for all other instructions. Each execution stage of the execution pipeline keeps track of the MRI bit flag information for the instruction. A writeback unit updates the status register after the execution of the instruction that has its MRI bit flag set. The writeback unit does not update the status register for instructions that have their MRI bit flag reset. This allows the instruction to be identified that is the most recent instruction to enter the dispatch unit.

Abstract: A floating point unit comprising: 1) an execution pipeline comprising a plurality of execution stages for executing floating point operations in a series of sequential steps; and 2) a try-again reservation station for storing a plurality of instructions to be loaded into the execution pipeline. Detection of a denormal result in the execution pipeline causes the execution pipeline to store the denormal result in a register array associated with the floating point unit and causes the execution pipeline to store a denormal result instruction in the try-again reservation station. The try-again reservation station subsequently re-loads the denormal result instruction into the execution pipeline and the de-normal result instruction retrieves the denormal result from the register array for additional processing.

Abstract: An electronic device and method of manufacturing the electronic device are disclosed herein. The electronic device comprises a substrate with at least a first and a second linear optical component mounted thereto. Each of the linear optical components includes a photodetecting portion and an interface portion, wherein the photodetecting portions are electrically connected to the interface portions. The photodetecting portions of the linear optical components are aligned along a first axis. The interface portion of the at least one first linear optical component is offset from the first axis in a first direction. The interface portion of the at least one second linear optical component is offset from the first axis in a second direction, which is different from the first direction. This arrangement of optical components reduces the size of the electronic device, which in turn, reduces the size of any device that incorporates the electronic device.