Abstract: Die-to-die communication links for receiver integrated circuit dies within multi-die systems and related methods are disclosed for radio frequency (RF) receivers. The disclosed embodiments provide die-to-die communication links that allow for direct communication of operating parameters between receiver integrated circuit dies and other integrated circuit dies within a multi-die system so that the operation of receive path circuitry can be adjusted without requiring intervention from an external host processor integrated circuit. A variety of operating parameter information can be communicated through the die-to-die communication links so that the integrated circuit dies can quickly adjust to changing signal conditions without requiring intervention by the external host processor integrated circuit.

Abstract: In one form, an integrated receiver includes a tracking bandpass filter, a tunable lowpass filter, and a mixer formed on a single integrated circuit chip. The tracking bandpass filter has an input for receiving a radio frequency (RF) input signal, and an output, and comprises a variable capacitor having a capacitance that varies in response to a bandpass frequency control signal, in parallel with an integrated inductor. The integrated inductor comprises a plurality of windings formed in a plurality of metal layers. The tunable lowpass filter has an input coupled to the output of the tracking bandpass filter, and an output and having a tuning input for receiving a cutoff frequency signal. The mixer has a signal input coupled to the output of the tunable lowpass filter, a local oscillator input for receiving a local oscillator signal, and a signal output for providing a converted RF signal.

Abstract: In one form, an integrated receiver includes a tracking bandpass filter, a tunable lowpass filter, and a mixer formed on a single integrated circuit chip. The tracking bandpass filter has an input for receiving a radio frequency (RF) input signal, and an output, and comprises a variable capacitor having a capacitance that varies in response to a bandpass frequency control signal, in parallel with an integrated inductor. The integrated inductor comprises a plurality of windings formed in a plurality of metal layers. The tunable lowpass filter has an input coupled to the output of the tracking bandpass filter, and an output and having a tuning input for receiving a cutoff frequency signal. The mixer has a signal input coupled to the output of the tunable lowpass filter, a local oscillator input for receiving a local oscillator signal, and a signal output for providing a converted RF signal.

Abstract: A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits.

Abstract: Die-to-die communication links for receiver integrated circuit dies within multi-die systems and related methods are disclosed for radio frequency (RF) receivers. The disclosed embodiments provide die-to-die communication links that allow for direct communication of operating parameters between receiver integrated circuit dies and other integrated circuit dies within a multi-die system so that the operation of receive path circuitry can be adjusted without requiring intervention from an external host processor integrated circuit. A variety of operating parameter information can be communicated through the die-to-die communication links so that the integrated circuit dies can quickly adjust to changing signal conditions without requiring intervention by the external host processor integrated circuit.

Abstract: An integrated receiver includes a first signal processing path, a second signal processing path, and a controller. The first signal processing path has an input and an output for providing a first processed signal, and comprises a first tracking bandpass filter having a first integrated inductor formed with windings in a first number of metal layers of the integrated receiver. The second signal processing path has an input and an output for providing a second processed signal, and comprises a second tracking bandpass filter having a second integrated inductor formed with windings in a second number of metal layers of the integrated receiver. The second number of windings is lower than the first number. The controller enables one of the first and second signal processing paths corresponding to a selected channel of a radio frequency (RF) input signal to provide an output signal.

Abstract: A receiver circuit includes an analog front-end and a digital processing unit. The analog front-end includes an input for receiving a radio frequency (RF) signal, a first control input for receiving a gain adjustment signal, a second control input for receiving a timing signal, and a signal output for providing a digital intermediate frequency (IF) signal. The analog front-end updates gains of a plurality of gain stages according to the gain adjustment signal and in synchronism with the timing signal. The digital processing unit is configured to produce at least one output signal derived from the digital IF signal. The digital processing unit includes a timing recovery circuit configured to generate the timing signal based on the digital IF signal to control timing of the updating gains of each of the plurality of adjustable gain stages.

Abstract: An integrated receiver includes a first signal processing path, a second signal processing path, and a controller. The first signal processing path has an input and an output for providing a first processed signal, and comprises a first tracking bandpass filter having a first integrated inductor formed with windings in a first number of metal layers of the integrated receiver. The second signal processing path has an input and an output for providing a second processed signal, and comprises a second tracking bandpass filter having a second integrated inductor formed with windings in a second number of metal layers of the integrated receiver. The second number of windings is lower than the first number. The controller enables one of the first and second signal processing paths corresponding to a selected channel of a radio frequency (RF) input signal to provide an output signal.

Abstract: A receiver includes an input section, a plurality of RF sections, an output circuit, and a controller. The input section receives and amplifies a radio frequency (RF) input signal to provide an amplified RF signal, and has a gain input. The plurality of RF sections each have an input for receiving the amplified RF signal, and an output for providing an intermediate frequency signal. The output circuit provides an intermediate frequency output signal in response to an output of at least one of the plurality of RF sections. The controller has an output coupled to the gain input of the input section.

Abstract: A receiver includes an input section, a plurality of RF sections, an output circuit, and a controller. The input section receives and amplifies a radio frequency (RF) input signal to provide an amplified RF signal, and has a gain input. The plurality of RF sections each have an input for receiving the amplified RF signal, and an output for providing an intermediate frequency signal. The output circuit provides an intermediate frequency output signal in response to an output of at least one of the plurality of RF sections. The controller has an output coupled to the gain input of the input section.

Abstract: An integrated wideband receiver includes first and second signal processing paths and a controller. The first signal processing path has an input, and an output for providing a first processed signal, and comprises a first tracking bandpass filter having a first integrated inductor. The second signal processing path has an input, and an output for providing a second processed signal, and comprises a second tracking bandpass filter having a second integrated inductor. The controller is for enabling one of the first and second signal processing paths corresponding to a selected channel of a radio frequency (RF) input signal to provide an output signal. The controller, the first integrated inductor, and said second integrated inductor are formed on a single integrated circuit chip.

Abstract: Systems and methods are disclosed for automatic gain control (AGC) for analog television signals using feed-forward signal path delay. Adjustments to the AGC frequency response are achieved by introducing an intentional delay in the signal path of sufficient length to allow time for measurement of a horizontal sync pulse level and for application of a feed-forward amplitude correction based upon this measurement to the same horizontal line.

Abstract: A receiver (100) includes a first element (110) with a signal input, a control input, a signal output, and gain steps of a first magnitude, a signal processing circuit (120-168) with a signal input coupled to the first element, and a signal output, a second element (180) that has a signal input coupled to signal processing circuit, a control input, a signal output, and gain steps of a second magnitude smaller than the first magnitude, and a controller (180) that has a control output coupled to the first element (110), a control output coupled to the second element (180), and that adjusts receiver (100) gain by changing the first element (110) gain by a first magnitude, changing the second element (180) gain by substantially an inverse first magnitude, and subsequently changing the gain of the second element (180) by steps of the second magnitude to achieve a desired gain.

Abstract: A receiver (400) includes a tracking bandpass filter (420) and a signal processing circuit (430-480). The tracking bandpass filter (420) has a first input for receiving a radio frequency (RF) signal, and an output, and includes a first portion (731) on a semiconductor die (730), and at least one inductor (721). The at least one inductor (721) is operatively coupled to the first portion of the tracking bandpass filter (420). The signal processing circuit (430-480) has an input coupled to the output of the tracking bandpass filter (420), and an output for providing a processed signal. The semiconductor die (730) and the at least one inductor (721) are integrated into a single multi-chip module (MCM) (710).

Abstract: An integrated wideband receiver includes first and second signal processing paths and a controller. The first signal processing path has an input, and an output for providing a first processed signal, and comprises a first tracking bandpass filter having a first integrated inductor. The second signal processing path has an input, and an output for providing a second processed signal, and comprises a second tracking bandpass filter having a second integrated inductor. The controller is for enabling one of the first and second signal processing paths corresponding to a selected channel of a radio frequency (RF) input signal to provide an output signal. The controller, the first integrated inductor, and said second integrated inductor are formed on a single integrated circuit chip.

Abstract: A receiver circuit includes an analog front-end and a digital processing unit. The analog front-end includes an input for receiving a radio frequency (RF) signal, a first control input for receiving a gain adjustment signal, a second control input for receiving a timing signal, and a signal output for providing a digital intermediate frequency (IF) signal. The analog front-end updates gains of a plurality of gain stages according to the gain adjustment signal and in synchronism with the timing signal. The digital processing unit is configured to produce at least one output signal derived from the digital IF signal. The digital processing unit includes a timing recovery circuit configured to generate the timing signal based on the digital IF signal to control timing of the updating gains of each of the plurality of adjustable gain stages.

Abstract: A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits.

Abstract: A receiver (1000) includes a direct digital frequency synthesizer (DDFS) (700) and first (1040) and second (1042) mixers. The DDFS (700) has a first output for providing a first local oscillator signal, and a second output for providing a second local oscillator signal offset from a quadrature relationship with the first local oscillator signal by a phase offset. The first mixer (1040) has a first input for receiving a radio frequency (RF) signal, a second input for receiving the first local oscillator signal, and an output for providing an in-phase signal at another frequency. The second mixer (1042) has a first input for receiving the RF signal, a second input for receiving the second local oscillator signal, and an output for providing a quadrature signal at the other frequency. The DDFS (700) may be implemented using first (702) and second (704) memories storing portions of a sinusoidal waveform and extra memories (706, 708) supporting the phase offset.

Abstract: A receiver (100) includes a first element (110) with a signal input, a control input, a signal output, and gain steps of a first magnitude, a signal processing circuit (120-168) with a signal input coupled to the first element, and a signal output, a second element (180) that has a signal input coupled to signal processing circuit, a control input, a signal output, and gain steps of a second magnitude smaller than the first magnitude, and a controller (180) that has a control output coupled to the first element (110), a control output coupled to the second element (180), and that adjusts receiver (100) gain by changing the first element (110) gain by a first magnitude, changing the second element (180) gain by substantially an inverse first magnitude, and subsequently changing the gain of the second element (180) by steps of the second magnitude to achieve a desired gain.

Abstract: A receiver (400) includes a tracking bandpass filter (420) and a signal processing circuit (430-480). The tracking bandpass filter (420) has a first input for receiving a radio frequency (RF) signal, and an output, and includes a first portion (731) on a semiconductor die (730), and at least one inductor (721). The at least one inductor (721) is operatively coupled to the first portion of the tracking bandpass filter (420). The signal processing circuit (430-480) has an input coupled to the output of the tracking bandpass filter (420), and an output for providing a processed signal. The semiconductor die (730) and the at least one inductor (721) are integrated into a single multi-chip module (MCM) (710).