Patents by Inventor David S. Walker

David S. Walker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10908841
    Abstract: Presented herein are methodologies for increasing effective throughput on a network. A method includes receiving a command request via a communication bus, the command request including a command ID, determining, based on the command ID, whether data in the command request is to be joined with data from other command requests having the same command ID, when it is determined, based on the command ID, that the data in the command request is to be joined with other data from other command requests having the same command ID, writing the data to a selected buffer in which the other data is already stored, and causing the data and the other data in the buffer to be sent as a payload of a single packet across a communications fabric.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: February 2, 2021
    Assignee: Cisco Technology, Inc.
    Inventors: Ravikiran Kaidala Lakshman, Deepak Srinivas Mayya, Tanjore K. Suresh, David S. Walker, Sagar Borikar, Shrikant Vaidya
  • Patent number: 10884960
    Abstract: In one embodiment, a direct memory access (DMA) controller within a host device obtains a packet to be processed by the host device, where the host device comprises a host processor, a network interface controller (NIC), and a co-processor of the NIC, and where the co-processor is configured to perform one or more specific packet processing operations. The DMA controller may then detect a DMA descriptor of the packet, and can determine, according to the DMA descriptor, how the packet is to be moved for processing within the host device. As such, the DMA controller may then move the packet, based on the determining, to one of either a host main memory, a NIC memory, or a co-processor memory of the host device.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: January 5, 2021
    Assignee: Cisco Technology, Inc.
    Inventors: Tanjore K. Suresh, David S. Walker, Ravi Shankar Palagummi, RaviKiran Kaidala Lakshman, Kar Wai Kam
  • Publication number: 20200334184
    Abstract: In one embodiment, a direct memory access (DMA) controller within a host device obtains a packet to be processed by the host device, where the host device comprises a host processor, a network interface controller (NIC), and a co-processor of the NIC, and where the co-processor is configured to perform one or more specific packet processing operations. The DMA controller may then detect a DMA descriptor of the packet, and can determine, according to the DMA descriptor, how the packet is to be moved for processing within the host device. As such, the DMA controller may then move the packet, based on the determining, to one of either a host main memory, a NIC memory, or a co-processor memory of the host device.
    Type: Application
    Filed: April 19, 2019
    Publication date: October 22, 2020
    Inventors: Tanjore K. Suresh, David S. Walker, Ravi Shankar Palagummi, RaviKiran Kaidala Lakshman, Kar Wai Kam
  • Publication number: 20200097212
    Abstract: Presented herein are methodologies for increasing effective throughput on a network. A method includes receiving a command request via a communication bus, the command request including a command ID, determining, based on the command ID, whether data in the command request is to be joined with data from other command requests having the same command ID, when it is determined, based on the command ID, that the data in the command request is to be joined with other data from other command requests having the same command ID, writing the data to a selected buffer in which the other data is already stored, and causing the data and the other data in the buffer to be sent as a payload of a single packet across a communications fabric.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Inventors: Ravikiran Kaidala Lakshman, Deepak Srinivas Mayya, Tanjore K. Suresh, David S. Walker, Sagar Borikar, Shrikant Vaidya
  • Patent number: 8958418
    Abstract: Various techniques can be used to handle frames within multi-stage switching fabric. For example, in one method, a frame and an associated frame header are received at a switching fabric stage. The associated frame header includes a first field and a second field. The method selects one or more fabric points of exit within the switching fabric stage, based on the second field. The first field is used to select one or more other fabric points of exit within another switching fabric stage, and thus two different fields within the associated frame header specify fabric points of exit. The method then sends the frame to the selected fabric points of exit within the switching fabric stage.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: February 17, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Kenneth M. Rose, David S. Walker, Vijay A. Nebhrajani, Ranganathan Rajagopalan
  • Patent number: 8904513
    Abstract: The method can be implemented on a processor executing software instructions stored in memory. In one embodiment of the invention, the method includes receiving an Ethernet frame, wherein the Ethernet frame comprises a Transmission Control Protocol (TCP) header, wherein the TCP header comprises a TCP header length value. When the Ethernet frame is received, the TCP header length value is compared to a predetermined value.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: December 2, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Kenneth M. Rose, Venkateshwar R. Pullela, David S. Walker, Kevin C. Wong, Kaichuan He, Yu Kwong Ng
  • Patent number: 8880746
    Abstract: An apparatus and method for unconditionally loading a value into first memory of an first integrated circuit, which operates in one of several different modes depending on value stored in the first memory. In one embodiment, apparatus comprises a printed circuit board. The first integrated circuit (IC) is mounted on the printed circuit board, wherein the first IC comprises a first memory device, and wherein the first IC is configured to operate in a first mode when a first value is stored in the first memory device, and wherein the first IC is configured to operate in a second mode when a second value is stored in the first memory device. The printed circuit board also includes a second IC mounted thereon. The second IC comprises a second memory device that stores the first value.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: November 4, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Kenneth M. Rose, David S. Walker
  • Patent number: 8625624
    Abstract: A self-adjusting load balancing among multiple fabric ports. A plurality of first values is received in response to receiving a first frame, wherein each of the first values is related to a quantity of data stored in a respective one of a plurality of buffers of fabric ports. First identifiers are also received, each of which corresponds to a respective one of a first subset of the plurality of buffers. A subset of the first identifiers is selected based on one or more of the first values. Thereafter one of the first identifiers contained in the selected subset is selected. Ultimately the first frame is transmitted to the buffer that corresponds to the selected one of the first identifiers.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: January 7, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Kenneth M. Rose, David S. Walker, Vijay A. Nebhrajani, Matthew Todd Lawson
  • Patent number: 8466711
    Abstract: In one embodiment, a programmable priority encoder is configured to receive inputs, including an ordered list of a plurality of input request values each representing either a request or a non-request, and a starting position within the ordered list of the plurality of input request values. The programmable priority encoder is configured to generate an identification of a result position of a first input indicating said request in order from a position identified from the starting position within the ordered list. In one embodiment, the programmable priority encoder includes a hierarchal structure of logic blocks including a plurality of columns of logic blocks; wherein a first-stage column of the plurality of columns of logic blocks is configured to operate on at most N input values; and wherein the ordered list of the plurality of input request values consists of N input request values.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: June 18, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: Vijay A. Nebhrajani, Kenneth Michael Rose, David S. Walker
  • Patent number: 8347199
    Abstract: A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header includes a CRC to provide improved error detection.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: January 1, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: Matthew Todd Lawson, David S. Walker
  • Patent number: 8332721
    Abstract: A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header includes a CRC to provide improved error detection.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: December 11, 2012
    Assignee: Cisco Technology, Inc.
    Inventors: Matthew Todd Lawson, David S. Walker
  • Publication number: 20120293199
    Abstract: In one embodiment, a programmable priority encoder is configured to receive inputs, including an ordered list of a plurality of input request values each representing either a request or a non-request, and a starting position within the ordered list of the plurality of input request values. The programmable priority encoder is configured to generate an identification of a result position of a first input indicating said request in order from a position identified from the starting position within the ordered list. In one embodiment, the programmable priority encoder includes a hierarchal structure of logic blocks including a plurality of columns of logic blocks; wherein a first-stage column of the plurality of columns of logic blocks is configured to operate on at most N input values; and wherein the ordered list of the plurality of input request values consists of N input request values.
    Type: Application
    Filed: May 19, 2011
    Publication date: November 22, 2012
    Applicant: Cisco Technology, Inc., a corporation of California
    Inventors: Vijay A. Nebhrajani, Kenneth Michael Rose, David S. Walker
  • Publication number: 20120294305
    Abstract: Various techniques can be used to handle frames within multi-stage switching fabric. For example, in one method, a frame and an associated frame header are received at a switching fabric stage. The associated frame header includes a first field and a second field. The method selects one or more fabric points of exit within the switching fabric stage, based on the second field. The first field is used to select one or more other fabric points of exit within another switching fabric stage, and thus two different fields within the associated frame header specify fabric points of exit. The method then sends the frame to the selected fabric points of exit within the switching fabric stage.
    Type: Application
    Filed: May 20, 2011
    Publication date: November 22, 2012
    Inventors: Kenneth M. Rose, David S. Walker, Vijay A. Nebhrajani, Ranganathan Rajagopalan
  • Patent number: 8296452
    Abstract: Disclosed is a method and apparatus for checking link layer protocol frames such as Ethernet frames. The method can be implemented on a processor executing software instructions stored in memory. In one embodiment of the invention, the method includes receiving an Ethernet frame, and counting data bytes of the Ethernet frame to generate a total number of counted bytes. The total number of counted bytes can be used to calculate a data length of a datagram of the Ethernet frame. Once calculated, the datagram data length can be compared to a predetermined value. If the datagram length does not fall within an acceptable range of the predetermined value, the Ethernet frame may be dropped so that the Ethernet frame does not reach its final destination.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: October 23, 2012
    Assignee: Cisco Technology, Inc.
    Inventors: Kenneth M. Rose, Venkateshwar R. Pullela, David S. Walker, Kevin C. Wong, Kaichuan He, Yu Kwong Ng
  • Patent number: 8155125
    Abstract: A method, system, and apparatus to transmit replicated multicast packets over a plurality of physical network links that are combined into one logical channel or link so that the replicated multicast packets are distributed over more than one network link is disclosed. It is further disclosed that distribution over the network links is accomplished, in part, through analyzing the multicast packet for information other than ethernet addresses. Such information can include a tag header including destination interface information.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: April 10, 2012
    Assignee: Cisco Technology, Inc.
    Inventors: Gaetano Borgione, Kevin C. Wong, David S. Walker, Chickayya Naik
  • Patent number: 7899048
    Abstract: A method is disclosed for remotely monitoring network traffic through a generic network. A first data packet, which indicates a first destination network element, is received. A second data packet, which contains at least a part of the first data packet, is generated. The second data packet indicates a second destination network element that is configured to monitor network traffic. The second destination network element differs from the first destination network element.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: March 1, 2011
    Assignee: Cisco Technology, Inc.
    Inventors: David S. Walker, Kalyan K. Ghosh, Thomas J. Edsall
  • Patent number: 7787464
    Abstract: An integrated circuit monitors the most active traffic flow rates on a communications network by using a leaky bucket model having a variable fill rate. As a switch receives packets, the packet identifications are sampled. A sampled packet identification is compared to record identifications in a table of identifications. If the sampled and record identifications match, an activity value for the packet identification is increased by an amount inversely proportional to an activity value associated with the record identification. If the sampled and record identifications do not match, the activity value is decreased. Record identifications are removed from the table when the activity value decreases to a specified level. New sampled identifications are added to the table if empty records exist.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: August 31, 2010
    Assignee: Cisco Technology, Inc.
    Inventors: David S. Walker, Daniel R. Ullum
  • Publication number: 20100185926
    Abstract: A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header includes a CRC to provide improved error detection.
    Type: Application
    Filed: January 21, 2009
    Publication date: July 22, 2010
    Inventors: Matthew Todd Lawson, David S. Walker
  • Publication number: 20100185919
    Abstract: A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header includes a CRC to provide improved error detection.
    Type: Application
    Filed: March 3, 2009
    Publication date: July 22, 2010
    Inventors: Matthew Todd Lawson, David S. Walker
  • Patent number: 7701949
    Abstract: An apparatus including a first buffer, a second buffer and a priority switch circuit. The first buffer is configured to store data of a first data stream having a first priority. The second buffer is configured to store data of a second data stream having a second priority. The priority switch circuit is coupled to the first buffer and the second buffer and is configured to interrupt a transmission of the first data stream from the first buffer upon detection of data of the second data stream and transmit data of the second data stream.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: April 20, 2010
    Assignee: Cisco Technology, Inc.
    Inventors: Kenneth M. Rose, David S. Walker, Michael A. Benning, Mick R. Jacobs