Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

Abstract: In an embodiment, a peripheral interface controller may include an inline cryptographic engine which may encrypt data being sent over a peripheral interface and decrypt data received from the peripheral interface. The encryption may be transparent to the device connected to the peripheral interface that is receiving/supplying the data. In an embodiment, the peripheral interface controller is included in a system on a chip (SOC) that also includes a memory controller configured to couple to a memory. The memory may be mounted on the SOC in a chip-on-chip or package-on-package configuration. The unencrypted data may be stored in the memory for use by other parts of the SOC (e.g. processors, on-chip peripherals, etc.). The keys used for the encryption/decryption of data may remain within the SOC.

Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

Abstract: In an embodiment, a peripheral interface controller may include an inline cryptographic engine which may encrypt data being sent over a peripheral interface and decrypt data received from the peripheral interface. The encryption may be transparent to the device connected to the peripheral interface that is receiving/supplying the data. In an embodiment, the peripheral interface controller is included in a system on a chip (SOC) that also includes a memory controller configured to couple to a memory. The memory may be mounted on the SOC in a chip-on-chip or package-on-package configuration. The unencrypted data may be stored in the memory for use by other parts of the SOC (e.g. processors, on-chip peripherals, etc.). The keys used for the encryption/decryption of data may remain within the SOC.

Abstract: A method of driving an electro-optic display comprising providing a current source, digitally modulating the current source and generating a modulated digital signal, and converting the modulated digital signal into an effective analog drive signal so that the display pixels receive an effective analog drive current, wherein the internal capacitance of the electro-optic display smooths the digitally modulated signal and generates the effective analog drive signal.

Abstract: A clock divider may provide a lower speed clock to a logic block portion, but during reset, the clock divider may not operate properly, causing the logic block portion to be reset at a clock frequency greater than the frequency for which that logic was designed. However, an extended reset may be employed in which the clock divider is reset normally first before the logic block portion, allowing that logic to be reset according to the divided clock (e.g., rather than a higher speed clock). An asynchronous reset may also be employed in which one or more clock dividers first emerge from reset before being provided with a (synchronized) high speed clock signal, causing the clock dividers to be in phase with each other. This may enable communication between different areas of an IC that might not otherwise be in proper phase with each other.

Abstract: A clock divider may provide a lower speed clock to a logic block portion, but during reset, the clock divider may not operate properly, causing the logic block portion to be reset at a clock frequency greater than the frequency for which that logic was designed. However, an extended reset may be employed in which the clock divider is reset normally first before the logic block portion, allowing that logic to be reset according to the divided clock (e.g., rather than a higher speed clock). An asynchronous reset may also be employed in which one or more clock dividers first emerge from reset before being provided with a (synchronized) high speed clock signal, causing the clock dividers to be in phase with each other. This may enable communication between different areas of an IC that might not otherwise be in proper phase with each other.

Abstract: A system for storing and disseminating knowledge contained in documents includes a document annotator that creates a structured syntactic textual model of each of the documents, an ontology directed extractor that extracts properties from the textual models, a database for storing the textual models and the properties, and an interface permitting queries to the database. The document annotator includes a plurality of data transformers and a plurality of custom annotator tools. The ontology directed extractor includes an ontology based schema definition and a plurality of ontology based data transformers. The interface includes a plurality of XSLT style sheets selectable according to context.

Abstract: An apparatus includes a first unit and a second functional units operating in a master-slave configuration. The first and second functional units operate as a master and slave, respectively. The first functional unit conveys clock and framing signals to the second functional unit. The second functional unit includes a buffer and a multiplexer having inputs coupled to the buffer. Digital audio data may be prefetched into the buffer. When a controller of the second functional unit detects assertion of the framing signal, it may cause a change of state to a selection signal provided to the multiplexer. Responsive thereto, the multiplexer selects an input coupled to receive, from the buffer, a next frame of data to be transmitted. A first bit of the frame is transmitted to the first functional unit on the same clock cycle in which assertion of the framing signal was detected.

Abstract: A method and apparatus for scaling a DLL code for a slave DLL operating at a different frequency than a master DLL is disclosed. An apparatus includes a master DLL coupled to receive a first clock signal and a group of series-coupled slave DLLs coupled to receive a second clock signal. The master DLL may provide a specified fraction of a cycle of the first clock signal. Scaling circuitry coupled between the master DLL and the group of slave DLLs may determine a ratio of frequencies of the first clock signal to the second clock signal. Based on the ratio and a delay code from the first DLL, the scaling circuitry may generate an adjusted delay code received by the group of slave DLLs to set a delay for the second clock signal to the specified fraction.

Abstract: A method and apparatus for scaling a DLL code for a slave DLL operating at a different frequency than a master DLL is disclosed. An apparatus includes a master DLL coupled to receive a first clock signal and a group of series-coupled slave DLLs coupled to receive a second clock signal. The master DLL may provide a specified fraction of a cycle of the first clock signal. Scaling circuitry coupled between the master DLL and the group of slave DLLs may determine a ratio of frequencies of the first clock signal to the second clock signal. Based on the ratio and a delay code from the first DLL, the scaling circuitry may generate an adjusted delay code received by the group of slave DLLs to set a delay for the second clock signal to the specified fraction.

Abstract: An apparatus includes a first unit and a second functional units operating in a master-slave configuration. The first and second functional units operate as a master and slave, respectively. The first functional unit conveys clock and framing signals to the second functional unit. The second functional unit includes a buffer and a multiplexer having inputs coupled to the buffer. Digital audio data may be prefetched into the buffer. When a controller of the second functional unit detects assertion of the framing signal, it may cause a change of state to a selection signal provided to the multiplexer. Responsive thereto, the multiplexer selects an input coupled to receive, from the buffer, a next frame of data to be transmitted. A first bit of the frame is transmitted to the first functional unit on the same clock cycle in which assertion of the framing signal was detected.

Abstract: A method of driving an electro-optic display comprising providing a current source, digitally modulating the current source and generating a modulated digital signal, and converting the modulated digital signal into an effective analog drive signal so that the display pixels receive an effective analog drive current, wherein the internal capacitance of the electro-optic display smooths the digitally modulated signal and generates the effective analog drive signal.

Abstract: A user programmable deductive spreadsheet is implemented as an add-in to an existing mathematical spreadsheet program and allows the use of a logic programming language such as Prolog via a familiar spreadsheet interface. A syntax is provided whereby a set of multiple values can be stored in a cell and can be operated on recursively by an expression in another cell. Rows and columns can be given user defined names and cells can be referenced by row and column name. Cells can reference cells in other spreadsheets or can reference an entire spreadsheet in one cell. A cell expression can reference itself. Logical, arithmetic, and lifted operators are provided. Spreadsheets can be defined as a transformation of another spreadsheet. When no negative or aggregate operators are used in the cell expressions, the meaning of the spreadsheet is given in terms of least fixed points. Otherwise, the meaning is given in terms of perfect models.

Abstract: The invention includes methods and software tools for acquiring data from diverse sources, and structuring the data in a form that may be used to determine object equivalence. Practice of the invention includes one or more of the following tools: a data acquisition web agent creator, a web agent created by the web agent creator, an agent manager for deploying said web agent, and ontology-directed classifier, an ontology-directed extractor, and an ontology-directed matcher. The tools are example driven through a graphical user interface.

Abstract: The present invention provides a system, apparatus and method for filtering an image that produces output images having high resolution without visual discontinuity across a wide range of resize ratios. The invention includes a linear filter for source images requiring low magnification and a higher order filter for source images requiring high magnification. In the transition region an interpolation is performed between the linear and higher order filters to provide a smooth transition in filtering and magnification to produce an output image.