Abstract: A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

Abstract: A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

Abstract: A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

Abstract: A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

Abstract: Digital circuits, and other types of circuits, may be implemented using improved charge domain techniques based on modern silicon processing compatible with standard digital flows. An example of technology that can be used for charge domain digital flows are FINs (as used in FinFET) which can be modified to produce charge domain shift registers and charge domain digital logic. Also, novel notch based implementations which overcome limited potential range, speed, complex clocking and density issues of older generations of charge domain technology may be disclsoed. Such implementations can significantly improve performance, density and reduce power consumption of charge domain digital circuits, with the proper implants and process modifications.

Abstract: A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

Abstract: An interface output for a capacitive sensor has a circuit to sample an input signal from the capacitive sensor, convert the sampled input signal to a digital signal and having an adjustable gain.

Abstract: A charge domain sigma delta analog to digital converter (ADC) is taught. A combiner is taught which acts as a delta operator and the same structure is also separately used as an adder in an NTF. The charge coupled combiner has a source of an input charge from a wired pair of diodes which creates a replica charge which cannot be destroyed. An output charge domain shift register comprised of memory nodes is provided. A second charge domain shift register and wired device is provided which is used with said combiner to implement an NTF. A quantizer is taught using a barrier whose height represents a discrete charge threshold. An NTF coupled to the quantizer provides charge which will either exceed or not exceed said threshold. A thyristor will actuate a subtract or add function at the delta combiner depending on the quantizer level to act as the DAC function of the ADC.

Abstract: A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

Abstract: An event driven device has a network collecting data. A device is coupled to the network for determining changes in the data collected, wherein the device signals the network to process the data collected when the device determines desired changes in the data collected. In a second embodiment a level shift adjusts the band diagram of a spill and fill circuit to allow processing only if a change in input value occurs. This is extended to teach a means by which the subset of an image or incoming audio data might be used to trigger an event. It could also be used for always on operation at lower power than alternative solutions.

Abstract: A device to extract a unique recognition vector from a user has a sensor generating an electrical signal responsive to one of: muscle, skin or brain activity of the user. A spectral conversion mechanism converts the electrical signal into a spectral image. A machine learning device converts the spectral image into a recognition vector associated with the user.

Abstract: A device to extract physiological information has at least one laser emitter. At least one optical detector is used to detect a change in optical power absorption. The laser emitter and optical detector are wire bonded into a chip scale module.

Abstract: A neural network learning mechanism has a device which perturbs analog neurons to measure an error which results from perturbations at different points within the neural network and modifies weights and biases to converge to a target.

Abstract: A multiplier has a MOSFET in a common source configuration. A MOSFET current source is coupled to a drain terminal of the MOSFET. An inverter has an input coupled to the drain terminal of the MOSFET. An output of the inverter gates two currents whose current magnitudes are proportional. A first capacitor has a first terminal coupled to a first of the two currents and a gate of the MOSFET and a second terminal grounded. A second capacitor has a first terminal coupled to a second of the two currents and a second terminal coupled to the first of the two currents. The multiplier is first reset by discharging a gate capacitance of the MOSFET and then allowing it to be recharged to a Vt comparator threshold after which a charge is removed from the gate terminal of the MOSFET reducing a voltage on the gate terminal below the Vt comparator threshold, causing the two currents to be enabled until the Vt comparator threshold reaches a previous Vt comparator threshold and the inverter turns off the two currents.

Abstract: A neural network learning mechanism has a device which perturbs analog neurons to measure an error which results from perturbations at different points within the neural network and modifies weights and biases to converge to a target.

Abstract: A neural network learning mechanism has a device which perturbs analog neurons to measure an error which results from perturbations at different points within the neural network and modifies weights and biases to converge to a target.

Abstract: A neural network learning mechanism has a device which perturbs analog neurons to measure an error which results from perturbations at different points within the neural network and modifies weights and biases to converge to a target.

Abstract: A multiplier has a pair of charge reservoirs. The pair of charge reservoirs are connected in series. A first charge movement device induces charge movement to or from the pair of charge reservoirs at a same rate. A second charge movement device induces charge movement to or from one of the pair of reservoirs, the rate of charge movement programmed to one of add or remove charges at a rate proportional to the first charge movement device. The first charge movement device loads a first charge into a first of the pair of charge reservoirs during a first cycle. The first charge movement device and the second charge movement device remove charges at a proportional rate from the pair of charge reservoirs during a second cycle until the first of the pair of charge reservoirs is depleted of the first charge. The second charge reservoir thereafter holding the multiplied result.

Abstract: A multiplier has a pair of charge reservoirs. The pair of charge reservoirs are connected in series. A first charge movement device induces charge movement to or from the pair of charge reservoirs at a same rate. A second charge movement device induces charge movement to or from one of the pair of reservoirs, the rate of charge movement programmed to one of add or remove charges at a rate proportional to the first charge movement device. The first charge movement device loads a first charge into a first of the pair of charge reservoirs during a first cycle. The first charge movement device and the second charge movement device remove charges at a proportional rate from the pair of charge reservoirs during a second cycle until the first of the pair of charge reservoirs is depleted of the first charge. The second charge reservoir thereafter holding the multiplied result.

Abstract: A multiplier has a pair of charge reservoirs. The pair of charge reservoirs are connected in series. A first charge movement device induces charge movement to or from the pair of charge reservoirs at a same rate. A second charge movement device induces charge movement to or from one of the pair of reservoirs, the rate of charge movement programmed to one of add or remove charges at a rate proportional to the first charge movement device. The first charge movement device loads a first charge into a first of the pair of charge reservoirs during a first cycle. The first charge movement device and the second charge movement device remove charges at a proportional rate from the pair of charge reservoirs during a second cycle until the first of the pair of charge reservoirs is depleted of the first charge. The second charge reservoir thereafter holding the multiplied result.