Patents by Inventor David Schkolnik

David Schkolnik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for DQS postamble detection and drift compensation in a double data rate (DDR) physical interface
    Patent number: 7675811
    Abstract: Circuitry for reading from a double data rate type memory, the circuitry including control logic, a first bi-directional input/output interface (I/O) configured to be coupled to a data bus of a double data rate type memory and to receive therefrom a data transmission having a duration selected by the control logic, a second bi-directional input/output interface (I/O) configured to be coupled to a data strobe line of the double data rate type memory, a gate coupled to the second bi-directional input/output interface configured for controlling the duration of a data strobe signal received along the data strobe line in response to a data strobe masking gating signal and a data strobe masking gating signal modifier applying to the expected data receipt duration indicating signal a variable time delay such as to center the expected data receipt duration indicating signal about the midpoint of the duration of the data transmission.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: March 9, 2010
    Assignee: Chipx Incorporated
    Inventors: Lior Amarilio, David Schkolnik, Ophir Nadir
  • Method and apparatus for DQS postamble detection and drift compensation in a double data rate (DDR) physical interface
    Publication number: 20090251976
    Abstract: Circuitry for reading from a double data rate type memory, the circuitry including control logic, a first bi-directional input/output interface (I/O) configured to be coupled to a data bus of a double data rate type memory and to receive therefrom a data transmission having a duration selected by the control logic, a second bi-directional input/output interface (I/O) configured to be coupled to a data strobe line of the double data rate type memory, a gate coupled to the second bi-directional input/output interface configured for controlling the duration of a data strobe signal received along the data strobe line in response to a data strobe masking gating signal and a data strobe masking gating signal modifier applying to the expected data receipt duration indicating signal a variable time delay such as to center the expected data receipt duration indicating signal about the midpoint of the duration of the data transmission.
    Type: Application
    Filed: April 7, 2008
    Publication date: October 8, 2009
    Inventors: Lior Amarilio, David Schkolnik, Ophir Nadir